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    Searched refs:ImplicitDefine (Results 1 - 25 of 28) sorted by relevancy

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  /src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/
SIFrameLowering.cpp 172 .addReg(TargetReg, RegState::ImplicitDefine);
549 .addReg(ScratchRsrcReg, RegState::ImplicitDefine)
583 .addReg(ScratchRsrcReg, RegState::ImplicitDefine);
598 .addReg(ScratchRsrcReg, RegState::ImplicitDefine);
609 .addReg(ScratchRsrcReg, RegState::ImplicitDefine);
613 .addReg(ScratchRsrcReg, RegState::ImplicitDefine);
619 .addReg(ScratchRsrcReg, RegState::ImplicitDefine);
623 .addReg(ScratchRsrcReg, RegState::ImplicitDefine);
650 .addReg(ScratchRsrcReg, RegState::ImplicitDefine);
654 .addReg(ScratchRsrcReg, RegState::ImplicitDefine);
    [all...]
SIRegisterInfo.cpp 195 I.addReg(TmpVGPR, RegState::ImplicitDefine);
206 I.addReg(TmpVGPR, RegState::ImplicitDefine);
1173 MIB.addReg(ValueReg, RegState::ImplicitDefine);
1219 AccRead.addReg(ValueReg, RegState::ImplicitDefine);
1250 MIB.addReg(ValueReg, RegState::ImplicitDefine);
1340 MIB.addReg(SB.SuperReg, RegState::ImplicitDefine);
1427 MIB.addReg(SB.SuperReg, RegState::ImplicitDefine);
1454 MIB.addReg(SB.SuperReg, RegState::ImplicitDefine);
SILowerControlFlow.cpp 228 .addReg(Exec, RegState::ImplicitDefine);
SIInstrInfo.cpp 1823 .addReg(VecReg, RegState::ImplicitDefine)
1857 .addReg(VecReg, RegState::ImplicitDefine)
  /src/external/apache2/llvm/dist/llvm/lib/Target/SystemZ/
SystemZElimCompare.cpp 236 MIB.addReg(SystemZ::CC, RegState::ImplicitDefine | RegState::Dead);
682 RegState::ImplicitDefine | RegState::Dead);
SystemZShortenInst.cpp 147 .addReg(SystemZ::CC, RegState::ImplicitDefine | RegState::Dead);
SystemZFrameLowering.cpp 308 MIB.addReg(Reg, RegState::ImplicitDefine);
SystemZInstrInfo.cpp 223 .addReg(Reg64, RegState::ImplicitDefine);
  /src/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/
MachineInstrBuilder.h 63 ImplicitDefine = Implicit | Define,
  /src/external/apache2/llvm/dist/llvm/lib/Target/ARM/
Thumb2InstrInfo.cpp 243 MIB.addReg(DestReg, RegState::ImplicitDefine);
ARMFrameLowering.cpp 1481 .addReg(SupReg, RegState::ImplicitDefine)
1498 .addReg(SupReg, RegState::ImplicitDefine)
ARMExpandPseudoInsts.cpp 627 MIB.addReg(DstReg, RegState::ImplicitDefine | getDeadRegState(DstIsDead));
795 MIB.addReg(DstReg, RegState::ImplicitDefine | getDeadRegState(DstIsDead));
2528 MIB.addReg(DstReg, RegState::ImplicitDefine | getDeadRegState(DstIsDead));
ARMBaseInstrInfo.cpp 1429 MIB.addReg(DestReg, RegState::ImplicitDefine);
1475 MIB.addReg(DestReg, RegState::ImplicitDefine);
1499 MIB.addReg(DestReg, RegState::ImplicitDefine);
1519 MIB.addReg(DestReg, RegState::ImplicitDefine);
ARMLoadStoreOptimizer.cpp 958 MIB.addReg(ImpDef, RegState::ImplicitDefine);
  /src/external/apache2/llvm/dist/llvm/lib/Target/M68k/
M68kFrameLowering.cpp 891 I.addReg(Info.getReg(), RegState::ImplicitDefine);
M68kInstrInfo.cpp 536 .addReg(Reg, RegState::ImplicitDefine)
  /src/external/apache2/llvm/dist/llvm/lib/Target/Mips/
MipsFastISel.cpp 2139 .addReg(Mips::HI0, RegState::ImplicitDefine | RegState::Dead)
2140 .addReg(Mips::LO0, RegState::ImplicitDefine | RegState::Dead);
MipsSEInstrInfo.cpp 134 .addReg(DestReg, RegState::ImplicitDefine);
MipsSEISelDAGToDAG.cpp 57 IsDef ? RegState::ImplicitDefine : RegState::Implicit | RegState::Undef;
  /src/external/apache2/llvm/dist/llvm/lib/CodeGen/SelectionDAG/
InstrEmitter.cpp 999 MIB.addReg(ScratchRegs[i], RegState::ImplicitDefine |
  /src/external/apache2/llvm/dist/llvm/lib/Target/PowerPC/
PPCInstrInfo.cpp 2171 .addReg(Pred[1].getReg(), RegState::ImplicitDefine);
2194 .addReg(Pred[1].getReg(), RegState::ImplicitDefine);
2251 .addReg(isPPC64 ? PPC::LR8 : PPC::LR, RegState::ImplicitDefine);
3180 .addImm(LII.Imm).addReg(PPC::CR0, RegState::ImplicitDefine);
PPCISelLowering.cpp 12393 .addReg(PPC::RM, RegState::ImplicitDefine);
12397 .addReg(PPC::RM, RegState::ImplicitDefine);
12464 .addReg(PPC::RM, RegState::ImplicitDefine);
12468 .addReg(PPC::RM, RegState::ImplicitDefine);
  /src/external/apache2/llvm/dist/llvm/lib/Target/X86/
X86InstrInfo.cpp 4700 MIB.addReg(SrcReg, RegState::ImplicitDefine);
4729 MIB.addReg(SrcReg, RegState::ImplicitDefine);
4804 MIB.addReg(Reg, RegState::ImplicitDefine);
5267 .addReg(Reg, RegState::ImplicitDefine);
5276 .addReg(Reg, RegState::ImplicitDefine);
  /src/external/apache2/llvm/dist/llvm/lib/CodeGen/MIRParser/
MIParser.cpp 1391 Flags |= RegState::ImplicitDefine;
  /src/external/apache2/llvm/dist/llvm/lib/Target/VE/
VEISelLowering.cpp 2438 MIB.addReg(Reg, RegState::ImplicitDefine | RegState::Dead);

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