HomeSort by: relevance | last modified time | path
    Searched refs:InL (Results 1 - 2 of 2) sorted by relevancy

  /src/external/apache2/llvm/dist/llvm/lib/CodeGen/SelectionDAG/
LegalizeIntegerTypes.cpp 2254 SDValue InL, InH;
2255 GetExpandedInteger(N->getOperand(0), InL, InH);
2260 Lo = InL;
2265 EVT NVT = InL.getValueType();
2276 NVT, InL, DAG.getConstant(Amt - NVTBits, DL, ShTy));
2279 Hi = InL;
2281 Lo = DAG.getNode(ISD::SHL, DL, NVT, InL, DAG.getConstant(Amt, DL, ShTy));
2285 DAG.getNode(ISD::SRL, DL, NVT, InL,
2303 DAG.getNode(ISD::SRL, DL, NVT, InL,
2327 DAG.getNode(ISD::SRL, DL, NVT, InL,
    [all...]
  /src/external/apache2/llvm/dist/llvm/lib/CodeGen/GlobalISel/
LegalizerHelper.cpp 4352 Register InL = MRI.createGenericVirtualRegister(HalfTy);
4354 MIRBuilder.buildUnmerge({InL, InH}, MI.getOperand(1));
4357 MIRBuilder.buildMerge(MI.getOperand(0), {InL, InH});
4372 Hi = MIRBuilder.buildShl(NVT, InL,
4376 Hi = InL;
4378 Lo = MIRBuilder.buildShl(NVT, InL, MIRBuilder.buildConstant(AmtTy, Amt));
4382 NVT, InL, MIRBuilder.buildConstant(AmtTy, -Amt + NVTBits));
4398 auto OrLHS = MIRBuilder.buildLShr(NVT, InL, ShiftAmtConst);
4421 auto OrLHS = MIRBuilder.buildLShr(NVT, InL, ShiftAmtConst);
4476 Register InL = MRI.createGenericVirtualRegister(HalfTy)
    [all...]

Completed in 18 milliseconds