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    Searched refs:InVT (Results 1 - 15 of 15) sorted by relevancy

  /src/external/apache2/llvm/dist/llvm/lib/CodeGen/SelectionDAG/
LegalizeVectorTypes.cpp 1168 EVT InVT = InOp.getValueType();
1171 switch (getTypeAction(InVT)) {
1435 EVT InVT = Op.getValueType();
1436 if (InVT.isVector()) {
1439 if (getTypeAction(InVT) == TargetLowering::TypeSplitVector)
1917 EVT InVT = N->getOperand(OpNo).getValueType();
1918 if (getTypeAction(InVT) == TargetLowering::TypeSplitVector)
2335 EVT InVT = Lo.getValueType();
2338 InVT.getVectorElementCount());
2795 EVT InVT = InVec->getValueType(0)
    [all...]
LegalizeTypesGeneric.cpp 44 EVT InVT = InOp.getValueType();
48 switch (getTypeAction(InVT)) {
66 if (TLI.hasBigEndianPartOrdering(InVT, DL) !=
89 assert(!(InVT.getVectorNumElements() & 1) && "Unsupported BITCAST");
92 std::tie(LoVT, HiVT) = DAG.GetSplitDestVTs(InVT);
102 if (InVT.isVector() && OutVT.isInteger()) {
162 Align InAlign = DAG.getReducedAlign(InVT, /*UseABI=*/false);
165 SDValue StackPtr = DAG.CreateStackTemporary(InVT.getStoreSize(), Align);
LegalizeIntegerTypes.cpp 337 EVT InVT = InOp.getValueType();
338 EVT NInVT = TLI.getTypeToTransformTo(*DAG.getContext(), InVT);
343 switch (getTypeAction(InVT)) {
405 unsigned ShiftAmt = NInVT.getSizeInBits() - InVT.getSizeInBits();
1062 EVT InVT = N->getOperand(OpNo).getValueType();
1065 EVT SVT = getSetCCResultType(InVT);
1071 if (getTypeAction(InVT) == TargetLowering::TypePromoteInteger) {
1072 InVT = TLI.getTypeToTransformTo(*DAG.getContext(), InVT);
1073 SVT = getSetCCResultType(InVT);
    [all...]
SelectionDAG.cpp 3255 EVT InVT = Op.getOperand(0).getValueType();
3256 APInt InDemandedElts = DemandedElts.zextOrSelf(InVT.getVectorNumElements());
3267 EVT InVT = Op.getOperand(0).getValueType();
3268 APInt InDemandedElts = DemandedElts.zextOrSelf(InVT.getVectorNumElements());
3283 EVT InVT = Op.getOperand(0).getValueType();
3284 APInt InDemandedElts = DemandedElts.zextOrSelf(InVT.getVectorNumElements());
DAGCombiner.cpp 19294 EVT InVT = Vec.getValueType();
19306 if (InVT.isSimple() && NearestPow2 > 2 && MaxIndex < NearestPow2 &&
19310 InVT.getVectorElementType(), SplitSize);
19453 EVT InVT = EVT::getVectorVT(*DAG.getContext(), InSVT, NumElems);
19456 if (LegalTypes && !TLI.isTypeLegal(InVT))
19466 In = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, InVT, In,
20291 EVT InVT = V.getValueType();
20293 unsigned EltSize = InVT.getScalarSizeInBits();
20297 EVT EltVT = InVT.getVectorElementType();
20310 Src = DAG.getNode(ISD::TRUNCATE, SDLoc(N), InVT, Src)
    [all...]
LegalizeDAG.cpp 2098 EVT InVT = Node->getOperand(Node->isStrictFPOpcode() ? 1 : 0).getValueType();
2101 switch (InVT.getSimpleVT().SimpleTy) {
  /src/external/apache2/llvm/dist/llvm/utils/TableGen/
CodeGenDAGPatterns.h 276 bool MergeInTypeInfo(TypeSetByHwMode &Out, MVT::SimpleValueType InVT) {
277 return MergeInTypeInfo(Out, TypeSetByHwMode(InVT));
279 bool MergeInTypeInfo(TypeSetByHwMode &Out, ValueTypeByHwMode InVT) {
280 return MergeInTypeInfo(Out, TypeSetByHwMode(InVT));
  /src/external/apache2/llvm/dist/llvm/lib/Target/RISCV/
RISCVISelDAGToDAG.cpp 1099 MVT InVT = V.getSimpleValueType();
1107 if (InVT.isFixedLengthVector())
1108 InVT = TLI.getContainerForFixedLengthVector(InVT);
1114 InVT, SubVecContainerVT, Idx, TRI);
1125 unsigned InRegClassID = RISCVTargetLowering::getRegClassIDForVecVT(InVT);
RISCVISelLowering.cpp 4164 MVT InVT = Op.getOperand(0).getSimpleValueType();
4165 MVT ContainerVT = getContainerForFixedLengthVector(InVT);
  /src/external/apache2/llvm/dist/llvm/lib/Target/X86/
X86ISelLowering.cpp 6369 EVT InVT = In.getValueType();
6370 assert(VT.isVector() && InVT.isVector() && "Expected vector VTs.");
6377 if (InVT.getSizeInBits() > 128) {
6378 assert(VT.getSizeInBits() == InVT.getSizeInBits() &&
6380 unsigned Scale = VT.getScalarSizeInBits() / InVT.getScalarSizeInBits();
6383 InVT = In.getValueType();
6386 if (VT.getVectorNumElements() != InVT.getVectorNumElements())
20741 MVT InVT = In.getSimpleValueType();
20745 assert(VT.isVector() && InVT.isVector() && "Expected vector type");
20748 assert(VT.getVectorNumElements() == InVT.getVectorNumElements() &
    [all...]
  /src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/
AArch64ISelLowering.cpp 3242 EVT InVT = Op.getOperand(0).getValueType();
3252 unsigned NumElts = InVT.getVectorNumElements();
3255 if (InVT.getVectorElementType() == MVT::f16 &&
3265 uint64_t InVTSize = InVT.getFixedSizeInBits();
3269 DAG.getNode(Op.getOpcode(), dl, InVT.changeVectorElementTypeToInteger(),
3358 EVT InVT = In.getValueType();
3363 if (InVT.getVectorElementType() == MVT::i1) {
3366 EVT CastVT = getPromotedVTForPredicate(InVT);
3377 uint64_t InVTSize = InVT.getFixedSizeInBits();
3380 MVT::getVectorVT(MVT::getFloatingPointVT(InVT.getScalarSizeInBits())
    [all...]
AArch64ISelDAGToDAG.cpp 3445 EVT InVT = Node->getOperand(0).getValueType();
3446 if (VT.isScalableVector() || InVT.isFixedLengthVector())
3469 EVT InVT = Node->getOperand(1).getValueType();
3470 if (VT.isFixedLengthVector() || InVT.isScalableVector())
  /src/external/apache2/llvm/dist/llvm/lib/Target/SystemZ/
SystemZISelLowering.cpp 3326 EVT InVT = In.getValueType();
3341 if (InVT == MVT::i32 && ResVT == MVT::f32) {
3357 if (InVT == MVT::f32 && ResVT == MVT::i32) {
4479 MVT InVT = MVT::getVectorVT(MVT::getIntegerVT(InBytes * 8),
4481 Op0 = DAG.getNode(ISD::BITCAST, DL, InVT, Op0);
4482 Op1 = DAG.getNode(ISD::BITCAST, DL, InVT, Op1);
4486 Op = DAG.getNode(SystemZISD::PERMUTE_DWORDS, DL, InVT, Op0, Op1, Op2);
4492 Op = DAG.getNode(P.Opcode, DL, InVT, Op0, Op1);
4864 EVT InVT = MVT::getVectorVT(MVT::getIntegerVT(InBits),
4866 SDValue PackedOp = DAG.getNode(ISD::BITCAST, DL, InVT, Op)
    [all...]
  /src/external/apache2/llvm/dist/llvm/lib/Target/PowerPC/
PPCISelDAGToDAG.cpp 2929 EVT InVT = InputOp.getValueType();
2930 return SDValue(CurDAG->getMachineNode(InVT == MVT::i32 ? PPC::RLDICL_32 :
2931 PPC::RLDICL, dl, InVT, InputOp,
3074 EVT InVT = LHS.getValueType();
3075 bool Is32Bit = InVT == MVT::i32;
3083 dl, InVT, LHS, LHS), 0);
5360 EVT InVT = N->getOperand(0).getValueType();
5361 assert((InVT == MVT::i64 || InVT == MVT::i32) &&
5364 unsigned Opcode = (InVT == MVT::i64) ? PPC::ANDI8_rec : PPC::ANDI_rec
    [all...]
PPCISelLowering.cpp 8402 EVT InVT = Src.getValueType();
8405 isOperationCustom(Op.getOpcode(), InVT))

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