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    Searched refs:IndexVT (Results 1 - 7 of 7) sorted by relevancy

  /src/external/apache2/llvm/dist/llvm/lib/Target/RISCV/
RISCVISelDAGToDAG.cpp 129 bool IsStridedOrIndexed, SmallVectorImpl<SDValue> &Operands, MVT *IndexVT) {
139 if (IndexVT)
140 *IndexVT = Operands.back()->getSimpleValueType(0);
266 MVT IndexVT;
268 /*IsStridedOrIndexed*/ true, Operands, &IndexVT);
270 assert(VT.getVectorElementCount() == IndexVT.getVectorElementCount() &&
273 RISCVII::VLMUL IndexLMUL = RISCVTargetLowering::getLMUL(IndexVT);
274 unsigned IndexScalarSize = IndexVT.getScalarSizeInBits();
343 MVT IndexVT;
345 /*IsStridedOrIndexed*/ true, Operands, &IndexVT);
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RISCVISelDAGToDAG.h 79 MVT *IndexVT = nullptr);
RISCVISelLowering.cpp 1849 MVT IndexVT = VT.changeTypeToInteger();
1853 if (IndexVT.getScalarType().bitsGT(XLenVT)) {
1855 IndexVT = IndexVT.changeVectorElementType(MVT::i16);
1859 ContainerVT.changeVectorElementType(IndexVT.getScalarType());
1867 SDValue LHSIndices = DAG.getBuildVector(IndexVT, DL, GatherIndicesLHS);
1883 SDValue RHSIndices = DAG.getBuildVector(IndexVT, DL, GatherIndicesRHS);
4361 MVT IndexVT = Index.getSimpleValueType();
4364 assert(VT.getVectorElementCount() == IndexVT.getVectorElementCount() &&
4381 if (VT.bitsGE(IndexVT)) {
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  /src/external/apache2/llvm/dist/llvm/lib/Target/X86/
X86ISelDAGToDAG.cpp 5720 MVT IndexVT = IndexOp.getSimpleValueType();
5739 if (IndexVT == MVT::v4i32 && NumElts == 4 && EltSize == 32)
5741 else if (IndexVT == MVT::v8i32 && NumElts == 8 && EltSize == 32)
5743 else if (IndexVT == MVT::v16i32 && NumElts == 16 && EltSize == 32)
5745 else if (IndexVT == MVT::v4i32 && NumElts == 2 && EltSize == 64)
5747 else if (IndexVT == MVT::v4i32 && NumElts == 4 && EltSize == 64)
5749 else if (IndexVT == MVT::v8i32 && NumElts == 8 && EltSize == 64)
5751 else if (IndexVT == MVT::v2i64 && NumElts == 4 && EltSize == 32)
5753 else if (IndexVT == MVT::v4i64 && NumElts == 4 && EltSize == 32)
5755 else if (IndexVT == MVT::v8i64 && NumElts == 8 && EltSize == 32
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X86ISelLowering.cpp 5197 MVT IndexVT = MVT::getVT(I.getArgOperand(2)->getType());
5199 IndexVT.getVectorNumElements());
5209 MVT IndexVT = MVT::getVT(I.getArgOperand(2)->getType());
5211 IndexVT.getVectorNumElements());
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  /src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/
AArch64ISelLowering.cpp 8891 MVT IndexVT = MVT::v8i8;
8894 IndexVT = MVT::v16i8;
8898 SDValue V1Cst = DAG.getNode(ISD::BITCAST, DL, IndexVT, V1);
8899 SDValue V2Cst = DAG.getNode(ISD::BITCAST, DL, IndexVT, V2);
8906 ISD::INTRINSIC_WO_CHAIN, DL, IndexVT,
8908 DAG.getBuildVector(IndexVT, DL,
8914 ISD::INTRINSIC_WO_CHAIN, DL, IndexVT,
8916 DAG.getBuildVector(IndexVT, DL,
8922 // Shuffle = DAG.getNode(AArch64ISD::TBL2, DL, IndexVT, V1Cst, V2Cst,
8923 // DAG.getBuildVector(IndexVT, DL, &TBLMask[0]
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  /src/external/apache2/llvm/dist/llvm/lib/CodeGen/SelectionDAG/
LegalizeVectorTypes.cpp 4966 EVT IndexVT = Index.getValueType();
4968 IndexVT.getVectorElementType(), NumElts);

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