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Searched
refs:InitReg
(Results
1 - 4
of
4
) sorted by relevancy
/src/external/apache2/llvm/dist/llvm/lib/CodeGen/
ModuloSchedule.cpp
1260
// Map from <LoopReg,
InitReg
> to phi register for all created phis. Note that
1261
// this map is only used when
InitReg
is non-undef.
1263
// Map from LoopReg to phi register where the
InitReg
is undef.
1269
// Insert a phi that carries LoopReg from the loop body and
InitReg
otherwise.
1270
// If
InitReg
is not given it is chosen arbitrarily. It will either be undef
1272
Register phi(Register LoopReg, Optional<Register>
InitReg
= {},
1457
Register KernelRewriter::phi(Register LoopReg, Optional<Register>
InitReg
,
1460
if (
InitReg
.hasValue()) {
1461
auto I = Phis.find({LoopReg,
InitReg
.getValue()});
1471
//
InitReg
is either undef or no existing phi takes InitReg as input. Try an
[
all
...]
/src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/
AMDILCFGStructurizer.cpp
1186
// rather than headBlk will have undefined value in
initReg
.
1198
// new: headBlk => if () {
initReg
= 1; org trueBlk branch} else
1199
// {
initReg
= 0; org falseBlk branch }
1200
// => landBlk => if (
initReg
) {org trueBlk} else {org falseBlk}
1203
// if (
initReg
!=2) {...}
1205
// add
initReg
= initVal to headBlk
1295
Register
InitReg
=
1297
insertCondBranchBefore(LandBlk, I, R600::IF_PREDICATE_SET,
InitReg
,
1303
// predecessor rather than headBlk has valid value in
initReg
if
1312
// predecessor rather than headBlk has valid value in
initReg
i
[
all
...]
AMDGPURegisterBankInfo.cpp
744
Register
InitReg
= B.buildUndef(ResTy).getReg(0);
746
InitResultRegs.push_back(
InitReg
);
749
MRI.setRegBank(
InitReg
, *DefBank);
SIISelLowering.cpp
3496
unsigned
InitReg
, unsigned ResultReg, unsigned PhiReg,
3512
.addReg(
InitReg
)
3744
Register
InitReg
= MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass);
3746
BuildMI(MBB, I, DL, TII->get(TargetOpcode::IMPLICIT_DEF),
InitReg
);
3749
auto InsPt = loadM0FromVGPR(TII, MBB, MI,
InitReg
, PhiReg, Offset,
Completed in 29 milliseconds
Indexes created Mon Jun 15 00:25:07 UTC 2026