| /src/external/apache2/llvm/dist/llvm/lib/Target/XCore/Disassembler/ |
| XCoreDisassembler.cpp | 45 uint64_t &Size, uint16_t &Insn) {
52 Insn = (Bytes[0] << 0) | (Bytes[1] << 8);
57 uint64_t &Size, uint32_t &Insn) {
64 Insn =
92 unsigned Insn,
97 unsigned Insn,
102 unsigned Insn,
107 unsigned Insn,
112 unsigned Insn,
117 unsigned Insn,
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Analysis/ |
| InstructionPrecedenceTracking.cpp | 59 const Instruction *Insn) {
61 getFirstSpecialInstruction(Insn->getParent());
62 return MaybeFirstSpecial && MaybeFirstSpecial->comesBefore(Insn);
84 for (const Instruction &Insn : *BB)
85 if (isSpecialInstruction(&Insn)) {
86 assert(It->second == &Insn &&
130 const Instruction *Insn) const {
136 return !isGuaranteedToTransferExecutionToSuccessor(Insn);
140 const Instruction *Insn) const {
142 if (match(Insn, m_Intrinsic<Intrinsic::experimental_widenable_condition>())
[all...] |
| GuardUtils.cpp | 35 for (auto &Insn : *DeoptBB) {
36 if (match(&Insn, m_Intrinsic<Intrinsic::experimental_deoptimize>()))
38 if (Insn.mayHaveSideEffects())
|
| /src/external/apache2/llvm/dist/llvm/include/llvm/Analysis/ |
| InstructionPrecedenceTracking.h | 60 /// Returns true iff the first special instruction of \p Insn's block exists
61 /// and dominates \p Insn.
62 bool isPreceededBySpecialInstruction(const Instruction *Insn);
64 /// A predicate that defines whether or not the instruction \p Insn is
69 virtual bool isSpecialInstruction(const Instruction *Insn) const = 0;
113 /// Returns true if the first ICFI of Insn's block exists and dominates Insn.
114 bool isDominatedByICFIFromSameBlock(const Instruction *Insn) {
115 return isPreceededBySpecialInstruction(Insn);
118 bool isSpecialInstruction(const Instruction *Insn) const override
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/Lanai/Disassembler/ |
| LanaiDisassembler.cpp | 54 static DecodeStatus decodeRiMemoryValue(MCInst &Inst, unsigned Insn,
57 static DecodeStatus decodeRrMemoryValue(MCInst &Inst, unsigned Insn,
60 static DecodeStatus decodeSplsValue(MCInst &Inst, unsigned Insn,
63 static DecodeStatus decodeBranch(MCInst &Inst, unsigned Insn, uint64_t Address,
70 static DecodeStatus decodeShiftImm(MCInst &Inst, unsigned Insn,
76 uint32_t &Insn) {
84 Insn =
90 static void PostOperandDecodeAdjust(MCInst &Instr, uint32_t Insn) {
101 AluOp = (Insn >> 8) & 0x7;
105 AluOp |= 0x20 | (((Insn >> 3) & 0xf) << 1)
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/AVR/Disassembler/ |
| AVRDisassembler.cpp | 98 static DecodeStatus decodeFIOARr(MCInst &Inst, unsigned Insn,
101 static DecodeStatus decodeFIORdA(MCInst &Inst, unsigned Insn,
104 static DecodeStatus decodeFIOBIT(MCInst &Inst, unsigned Insn,
107 static DecodeStatus decodeCallTarget(MCInst &Inst, unsigned Insn,
110 static DecodeStatus decodeFRd(MCInst &Inst, unsigned Insn,
113 static DecodeStatus decodeFLPMX(MCInst &Inst, unsigned Insn,
116 static DecodeStatus decodeFFMULRdRr(MCInst &Inst, unsigned Insn,
119 static DecodeStatus decodeFMOVWRdRr(MCInst &Inst, unsigned Insn,
122 static DecodeStatus decodeFWRdK(MCInst &Inst, unsigned Insn,
125 static DecodeStatus decodeFMUL2RdRr(MCInst &Inst, unsigned Insn,
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/ |
| AArch64ExpandImm.h | 29 SmallVectorImpl<ImmInsnModel> &Insn);
|
| AArch64ExpandImm.cpp | 44 SmallVectorImpl<ImmInsnModel> &Insn) {
68 Insn.push_back({ AArch64::ORRXri, 0, Encoding });
81 Insn.push_back({ AArch64::MOVKXi, Imm16,
96 Insn.push_back({ AArch64::MOVKXi, Imm16,
152 SmallVectorImpl<ImmInsnModel> &Insn) {
224 Insn.push_back({ AArch64::ORRXri, 0, Encoding });
227 Insn.push_back({ AArch64::MOVKXi, getChunk(UImm, FirstMovkIdx),
236 Insn.push_back({ AArch64::MOVKXi, getChunk(UImm, SecondMovkIdx),
247 SmallVectorImpl<ImmInsnModel> &Insn) {
279 Insn.push_back({ FirstOpc, Imm16
[all...] |
| AArch64ExpandPseudoInsts.cpp | 134 SmallVector<AArch64_IMM::ImmInsnModel, 4> Insn;
135 AArch64_IMM::expandMOVImm(Imm, BitSize, Insn);
136 assert(Insn.size() != 0);
139 for (auto I = Insn.begin(), E = Insn.end(); I != E; ++I) {
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/ARC/Disassembler/ |
| ARCDisassembler.cpp | 51 uint64_t &Size, uint32_t &Insn) {
54 Insn =
60 uint64_t &Size, uint64_t &Insn) {
62 Insn = ((uint64_t)Bytes[0] << 16) | ((uint64_t)Bytes[1] << 24) |
70 uint64_t &Size, uint64_t &Insn) {
72 Insn = ((uint64_t)Bytes[0] << 0) | ((uint64_t)Bytes[1] << 8) |
79 uint64_t &Size, uint32_t &Insn) {
81 Insn = (Bytes[0] << 0) | (Bytes[1] << 8);
145 static unsigned decodeCField(unsigned Insn) {
146 return fieldFromInstruction(Insn, 6, 6)
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/Mips/Disassembler/ |
| MipsDisassembler.cpp | 113 unsigned Insn,
147 unsigned Insn,
217 unsigned Insn,
267 unsigned Insn,
274 unsigned Insn,
279 unsigned Insn,
284 unsigned Insn,
289 unsigned Insn,
293 static DecodeStatus DecodeCacheOp(MCInst &Inst, unsigned Insn, uint64_t Address,
297 unsigned Insn,
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/ARM/Disassembler/ |
| ARMDisassembler.cpp | 251 static DecodeStatus DecodeBitfieldMaskOperand(MCInst &Inst, unsigned Insn,
253 static DecodeStatus DecodeCopMemInstruction(MCInst &Inst, unsigned Insn,
256 unsigned Insn,
259 static DecodeStatus DecodeSORegMemOperand(MCInst &Inst, unsigned Insn,
261 static DecodeStatus DecodeAddrMode3Instruction(MCInst &Inst,unsigned Insn,
263 static DecodeStatus DecodeSORegImmOperand(MCInst &Inst, unsigned Insn,
265 static DecodeStatus DecodeSORegRegOperand(MCInst &Inst, unsigned Insn,
269 unsigned Insn,
272 static DecodeStatus DecodeT2MOVTWInstruction(MCInst &Inst, unsigned Insn,
274 static DecodeStatus DecodeArmMOVTWInstruction(MCInst &Inst, unsigned Insn,
[all...] |
| /src/external/apache2/llvm/dist/llvm/utils/TableGen/ |
| PseudoLoweringEmitter.cpp | 55 CodeGenInstruction &Insn,
73 addDagOperandMapping(Record *Rec, DagInit *Dag, CodeGenInstruction &Insn,
93 if (DI->getDef() != Insn.Operands[BaseIdx + i].Rec) {
97 Insn.Operands[BaseIdx + i].Rec->getName() + "'");
104 for (unsigned I = 0, E = Insn.Operands[i].MINumOperands; I != E; ++I)
106 OpsAdded += Insn.Operands[i].MINumOperands;
120 addDagOperandMapping(Rec, SubDag, Insn, OperandMap, BaseIdx + i);
155 CodeGenInstruction Insn(Operator);
157 if (Insn.isCodeGenOnly || Insn.isPseudo)
[all...] |
| FixedLenDecoderEmitter.cpp | 421 // Populates the insn given the uid.
422 void insnWithID(insn_t &Insn, unsigned Opcode) const {
435 Insn.push_back(BIT_UNSET);
437 Insn.push_back(bitFromBits(Bits, i));
450 // Populates the field of the insn given the start position and the number of
455 bool fieldFromInsn(uint64_t &Field, insn_t &Insn, unsigned StartBit,
483 const insn_t &Insn) const;
564 insn_t Insn;
566 // Populates the insn given the uid.
567 Owner->insnWithID(Insn, Owner->Opcodes[i].EncodingID)
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/MSP430/Disassembler/ |
| MSP430Disassembler.cpp | 181 static AddrMode DecodeSrcAddrModeI(unsigned Insn) {
182 unsigned Rs = fieldFromInstruction(Insn, 8, 4);
183 unsigned As = fieldFromInstruction(Insn, 4, 2);
187 static AddrMode DecodeSrcAddrModeII(unsigned Insn) {
188 unsigned Rs = fieldFromInstruction(Insn, 0, 4);
189 unsigned As = fieldFromInstruction(Insn, 4, 2);
193 static AddrMode DecodeDstAddrMode(unsigned Insn) {
194 unsigned Rd = fieldFromInstruction(Insn, 0, 4);
195 unsigned Ad = fieldFromInstruction(Insn, 7, 1);
233 uint64_t Insn = support::endian::read16le(Bytes.data())
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/BPF/Disassembler/ |
| BPFDisassembler.cpp | 126 static DecodeStatus decodeMemoryOpValue(MCInst &Inst, unsigned Insn,
128 unsigned Register = (Insn >> 16) & 0xf;
133 unsigned Offset = (Insn & 0xffff);
141 uint64_t &Size, uint64_t &Insn,
159 Insn = Make_64(Hi, Lo);
169 uint64_t Insn, Hi;
172 Result = readInstruction64(Bytes, Address, Size, Insn, IsLittleEndian);
175 uint8_t InstClass = getInstClass(Insn);
176 uint8_t InstMode = getInstMode(Insn);
178 getInstSize(Insn) != BPF_DW &
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/RISCV/Disassembler/ |
| RISCVDisassembler.cpp | 340 static DecodeStatus decodeRVCInstrSImm(MCInst &Inst, unsigned Insn,
343 static DecodeStatus decodeRVCInstrRdSImm(MCInst &Inst, unsigned Insn,
346 static DecodeStatus decodeRVCInstrRdRs1UImm(MCInst &Inst, unsigned Insn,
350 static DecodeStatus decodeRVCInstrRdRs2(MCInst &Inst, unsigned Insn,
353 static DecodeStatus decodeRVCInstrRdRs1Rs2(MCInst &Inst, unsigned Insn,
359 static DecodeStatus decodeRVCInstrSImm(MCInst &Inst, unsigned Insn,
362 fieldFromInstruction(Insn, 12, 1) << 5 | fieldFromInstruction(Insn, 2, 5);
369 static DecodeStatus decodeRVCInstrRdSImm(MCInst &Inst, unsigned Insn,
374 fieldFromInstruction(Insn, 12, 1) << 5 | fieldFromInstruction(Insn, 2, 5)
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/ExecutionEngine/RuntimeDyld/Targets/ |
| RuntimeDyldELFMips.cpp | 215 uint32_t Insn = readBytesUnaligned(TargetPtr, 4);
233 Insn = (Insn & 0xffff0000) | (Value & 0x0000ffff);
234 writeBytesUnaligned(Insn, TargetPtr, 4);
237 Insn = (Insn & 0xfffc0000) | (Value & 0x0003ffff);
238 writeBytesUnaligned(Insn, TargetPtr, 4);
241 Insn = (Insn & 0xfff80000) | (Value & 0x0007ffff);
242 writeBytesUnaligned(Insn, TargetPtr, 4)
[all...] |
| RuntimeDyldMachOARM.h | 272 uint32_t Insn = readBytesUnaligned(LocalAddress, 4);
275 Insn = (Insn & 0x8f00fbf0) | ((Value & 0xf000) >> 12) |
279 Insn = (Insn & 0xfff0f000) | ((Value & 0xf000) << 4) | (Value & 0x0fff);
280 writeBytesUnaligned(Insn, LocalAddress, 4);
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/X86/Disassembler/ |
| X86Disassembler.cpp | 178 static bool peek(struct InternalInstruction *insn, uint8_t &byte) {
179 uint64_t offset = insn->readerCursor - insn->startLocation;
180 if (offset >= insn->bytes.size())
182 byte = insn->bytes[offset];
186 template <typename T> static bool consume(InternalInstruction *insn, T &ptr) {
187 auto r = insn->bytes;
188 uint64_t offset = insn->readerCursor - insn->startLocation;
195 insn->readerCursor += sizeof(T)
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/MCTargetDesc/ |
| AArch64MCTargetDesc.cpp | 340 uint32_t Insn = support::endian::read32le(PltContents.data() + Byte);
343 if (Insn == 0xd503245f) {
345 Insn = support::endian::read32le(PltContents.data() + Byte + Off);
348 if ((Insn & 0x9f000000) != 0x90000000)
352 (((Insn >> 29) & 3) << 12) + (((Insn >> 5) & 0x3ffff) << 14);
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/Sparc/Disassembler/ |
| SparcDisassembler.cpp | 269 static DecodeStatus DecodeLoadInt(MCInst &Inst, unsigned insn, uint64_t Address,
271 static DecodeStatus DecodeLoadIntPair(MCInst &Inst, unsigned insn, uint64_t Address,
273 static DecodeStatus DecodeLoadFP(MCInst &Inst, unsigned insn, uint64_t Address,
275 static DecodeStatus DecodeLoadDFP(MCInst &Inst, unsigned insn, uint64_t Address,
277 static DecodeStatus DecodeLoadQFP(MCInst &Inst, unsigned insn, uint64_t Address,
279 static DecodeStatus DecodeLoadCP(MCInst &Inst, unsigned insn, uint64_t Address,
281 static DecodeStatus DecodeLoadCPPair(MCInst &Inst, unsigned insn, uint64_t Address,
283 static DecodeStatus DecodeStoreInt(MCInst &Inst, unsigned insn,
285 static DecodeStatus DecodeStoreIntPair(MCInst &Inst, unsigned insn,
287 static DecodeStatus DecodeStoreFP(MCInst &Inst, unsigned insn,
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Transforms/Scalar/ |
| GVNHoist.cpp | 464 << IDFBB->getName() << ", for Insn: " << *V[i]);
645 Instruction *Insn = MU->getMemoryInst();
648 if (BB == OldBB && firstInBB(OldPt, Insn))
654 if (firstInBB(Insn, NewPt))
810 Instruction *Insn = CHI.I;
811 if (!Insn) // No instruction was inserted in this CHI.
814 if (safeToHoistScalar(BB, Insn->getParent(), NumBBsOnAllPaths))
818 if (MemoryUseOrDef *UD = MSSA->getMemoryAccess(Insn))
819 if (safeToHoistLdSt(T, Insn, UD, K, NumBBsOnAllPaths))
|
| GuardWidening.cpp | 284 static bool isSupportedGuardInstruction(const Instruction *Insn) {
285 if (isGuard(Insn))
287 if (WidenBranchGuards && isGuardAsWidenableBranch(Insn))
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/VE/Disassembler/ |
| VEDisassembler.cpp | 213 static DecodeStatus DecodeASX(MCInst &Inst, uint64_t insn, uint64_t Address,
215 static DecodeStatus DecodeLoadI32(MCInst &Inst, uint64_t insn, uint64_t Address,
217 static DecodeStatus DecodeStoreI32(MCInst &Inst, uint64_t insn,
219 static DecodeStatus DecodeLoadI64(MCInst &Inst, uint64_t insn, uint64_t Address,
221 static DecodeStatus DecodeStoreI64(MCInst &Inst, uint64_t insn,
223 static DecodeStatus DecodeLoadF32(MCInst &Inst, uint64_t insn, uint64_t Address,
225 static DecodeStatus DecodeStoreF32(MCInst &Inst, uint64_t insn,
227 static DecodeStatus DecodeLoadASI64(MCInst &Inst, uint64_t insn,
229 static DecodeStatus DecodeStoreASI64(MCInst &Inst, uint64_t insn,
231 static DecodeStatus DecodeTS1AMI64(MCInst &Inst, uint64_t insn,
[all...] |
