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    Searched refs:InstDesc (Results 1 - 7 of 7) sorted by relevancy

  /src/external/apache2/llvm/dist/llvm/include/llvm/Analysis/
IVDescriptors.h 81 class InstDesc {
83 InstDesc(bool IsRecur, Instruction *I, Instruction *ExactFP = nullptr)
87 InstDesc(Instruction *I, RecurKind K, Instruction *ExactFP = nullptr)
118 static InstDesc isRecurrenceInstr(Instruction *I, RecurKind Kind,
119 InstDesc &Prev, FastMathFlags FMF);
133 static InstDesc isMinMaxSelectCmpPattern(Instruction *I,
134 const InstDesc &Prev);
138 static InstDesc isConditionalRdxPattern(RecurKind Kind, Instruction *I);
  /src/external/apache2/llvm/dist/llvm/lib/Analysis/
IVDescriptors.cpp 253 InstDesc ReduxDesc(false, nullptr);
347 // TODO: Can we eliminate the need for a 2nd InstDesc by keeping 'Kind'
416 InstDesc IgnoredVal(false, nullptr);
508 RecurrenceDescriptor::InstDesc
510 const InstDesc &Prev) {
519 return InstDesc(Select, Prev.getRecKind());
525 return InstDesc(false, I);
529 return InstDesc(I, RecurKind::UMin);
531 return InstDesc(I, RecurKind::UMax);
533 return InstDesc(I, RecurKind::SMax)
    [all...]
  /src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/
AArch64SIMDInstrOpt.cpp 157 /// to replace the instruction InstDesc by the instructions stored in the
160 bool shouldReplaceInst(MachineFunction *MF, const MCInstrDesc *InstDesc,
214 /// to replace the instruction InstDesc by the instructions stored in the
218 shouldReplaceInst(MachineFunction *MF, const MCInstrDesc *InstDesc,
223 auto InstID = std::make_pair(InstDesc->getOpcode(), Subtarget);
228 unsigned SCIdx = InstDesc->getSchedClass();
256 if (SchedModel.computeInstrLatency(InstDesc->getOpcode()) > ReplCost)
  /src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/
SIFoldOperands.cpp 449 const MCInstrDesc &InstDesc = MI->getDesc();
450 const MCOperandInfo &OpInfo = InstDesc.OpInfo[OpNo];
458 for (unsigned i = 0, e = InstDesc.getNumOperands(); i != e; ++i) {
1552 const MCInstrDesc &InstDesc = UseMI->getDesc();
1553 const MCOperandInfo &OpInfo = InstDesc.OpInfo[OpIdx];
SIInstrInfo.cpp 3430 const MCInstrDesc &InstDesc = MI.getDesc();
3431 const MCOperandInfo &OpInfo = InstDesc.OpInfo[OpNo];
3452 if (!isVOP3(MI) || !AMDGPU::isSISrcOperand(InstDesc, OpNo))
4632 const MCInstrDesc &InstDesc = MI.getDesc();
4633 const MCOperandInfo &OpInfo = InstDesc.OpInfo[OpIdx];
4656 usesConstantBus(MRI, Op, InstDesc.OpInfo[i])) {
4661 } else if (InstDesc.OpInfo[i].OperandType == AMDGPU::OPERAND_KIMM32) {
4664 } else if (isVOP3(MI) && AMDGPU::isSISrcOperand(InstDesc, i) &&
4665 isLiteralConstantLike(Op, InstDesc.OpInfo[i])) {
6335 const MCInstrDesc &InstDesc = get(Opcode)
    [all...]
  /src/external/apache2/llvm/dist/llvm/lib/Target/X86/MCTargetDesc/
X86AsmBackend.cpp 435 const MCInstrDesc &InstDesc = MCII->get(Jcc.getOpcode());
436 if (!InstDesc.isConditionalBranch())
  /src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/AsmParser/
AMDGPUAsmParser.cpp 1970 const auto& InstDesc = AsmParser->getMII()->get(Inst.getOpcode());
1973 assert(AMDGPU::isSISrcOperand(InstDesc, OpNum));
1976 assert(AMDGPU::isSISrcFPOperand(InstDesc, OpNum));
1977 const unsigned Size = Imm.IsFPImm ? sizeof(double) : getOperandSize(InstDesc, OpNum);
1982 uint8_t OpTy = InstDesc.OpInfo[OpNum].OperandType;
1999 if (AMDGPU::isSISrcFPOperand(InstDesc, OpNum)) { // Expected 64-bit fp operand

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