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    Searched refs:InstRWs (Results 1 - 3 of 3) sorted by relevancy

  /src/external/apache2/llvm/dist/llvm/utils/TableGen/
CodeGenSchedule.cpp 931 const RecVec &RWDefs = SchedClasses[SCIdx].InstRWs;
1065 const RecVec &RWDefs = SchedClasses[OldSCIdx].InstRWs;
1095 SchedClasses[OldSCIdx].InstRWs.push_back(InstRWDef);
1112 // If we had an old class, copy it's InstRWs to this new class.
1115 for (Record *OldRWDef : SchedClasses[OldSCIdx].InstRWs) {
1128 SC.InstRWs.push_back(OldRWDef);
1134 SC.InstRWs.push_back(InstRWDef);
1229 if (!SchedClasses[Idx].InstRWs.empty())
1265 for (unsigned I = 0, E = SchedClasses[SCIdx].InstRWs.size(); I != E; ++I) {
1266 assert(SchedClasses[SCIdx].InstRWs.size() == E && "InstrRWs was mutated!")
    [all...]
CodeGenSchedule.h 143 RecVec InstRWs;
144 // InstRWs processor indices. Filled in inferFromInstRWs
SubtargetEmitter.cpp 1025 if (!SC.InstRWs.empty()) {
1029 for (Record *RW : SC.InstRWs) {

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