| /src/external/apache2/llvm/dist/llvm/include/llvm/IR/ |
| ReplaceConstant.h | 23 /// it before \p Instr.
24 Instruction *createReplacementInstr(ConstantExpr *CE, Instruction *Instr);
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| /src/external/apache2/llvm/dist/llvm/lib/Target/ARM/ |
| ARMFeatures.h | 21 bool IsCPSRDead(const InstrType *Instr);
24 inline bool isV8EligibleForIT(const InstrType *Instr) {
25 switch (Instr->getOpcode()) {
52 return IsCPSRDead(Instr);
79 return Instr->getOperand(2).getReg() != ARM::PC;
84 return Instr->getOperand(0).getReg() != ARM::PC;
86 return Instr->getOperand(0).getReg() != ARM::PC &&
87 Instr->getOperand(2).getReg() != ARM::PC;
90 return Instr->getOperand(0).getReg() != ARM::PC &&
91 Instr->getOperand(1).getReg() != ARM::PC
[all...] |
| MVETPAndVPTOptimisationsPass.cpp | 71 MachineInstr &Instr,
536 static ARMCC::CondCodes GetCondCode(MachineInstr &Instr) {
537 assert(IsVCMP(Instr.getOpcode()) && "Inst must be a VCMP");
538 return ARMCC::CondCodes(Instr.getOperand(3).getImm());
568 // Returns true if Instr writes to VCCR.
569 static bool IsWritingToVCCR(MachineInstr &Instr) {
570 if (Instr.getNumOperands() == 0)
572 MachineOperand &Dst = Instr.getOperand(0);
578 MachineRegisterInfo &RegInfo = Instr.getMF()->getRegInfo();
584 // <Instr that uses %A ('User' Operand)
[all...] |
| /src/external/apache2/llvm/dist/llvm/tools/llvm-cfi-verify/lib/ |
| FileAnalysis.h | 78 struct Instr {
82 bool Valid; // Is this a valid instruction? If false, Instr::Instruction is
98 const Instr *getInstruction(uint64_t Address) const;
102 const Instr &getInstructionOrDie(uint64_t Address) const;
107 const Instr *getPrevInstructionSequential(const Instr &InstrMeta) const;
108 const Instr *getNextInstructionSequential(const Instr &InstrMeta) const;
111 bool isCFITrap(const Instr &InstrMeta) const;
115 bool willTrapOnCFIViolation(const Instr &InstrMeta) const
[all...] |
| GraphBuilder.h | 44 using Instr = llvm::cfi_verify::FileAnalysis::Instr;
130 const Instr &BranchInstrMeta);
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| FileAnalysis.cpp | 39 using Instr = llvm::cfi_verify::FileAnalysis::Instr;
121 const Instr *
122 FileAnalysis::getPrevInstructionSequential(const Instr &InstrMeta) const {
123 std::map<uint64_t, Instr>::const_iterator KV =
134 const Instr *
135 FileAnalysis::getNextInstructionSequential(const Instr &InstrMeta) const {
136 std::map<uint64_t, Instr>::const_iterator KV =
147 bool FileAnalysis::usesRegisterOperand(const Instr &InstrMeta) const {
155 const Instr *FileAnalysis::getInstruction(uint64_t Address) const
[all...] |
| /src/external/apache2/llvm/dist/llvm/tools/llvm-exegesis/lib/ |
| CodeTemplate.cpp | 18 InstructionTemplate::InstructionTemplate(const Instruction *Instr)
19 : Instr(Instr), VariableValues(Instr->Variables.size()) {}
32 return Instr->Description.getOpcode();
44 return getValueFor(Instr->Variables[Op.getVariableIndex()]);
48 return getValueFor(Instr->Variables[Op.getVariableIndex()]);
52 return any_of(Instr->Variables, [this](const Variable &Var) {
53 return Instr->getPrimaryOperand(Var).isImmediate();
59 Result.setOpcode(Instr->Description.Opcode)
[all...] |
| SerialSnippetGenerator.cpp | 38 computeAliasingInstructions(const LLVMState &State, const Instruction *Instr,
49 if (OtherOpcode == Instr->Description.getOpcode())
63 if (Instr->hasAliasingRegistersThrough(OtherInstr, ForbiddenRegisters))
71 static ExecutionMode getExecutionModes(const Instruction &Instr,
74 if (Instr.hasAliasingImplicitRegisters())
76 if (Instr.hasTiedRegisters())
78 if (Instr.hasMemoryOperands())
81 if (Instr.hasAliasingRegisters(ForbiddenRegisters))
83 if (Instr.hasOneUseOrOneDef())
121 "Instr must alias itself explicitly")
[all...] |
| CodeTemplate.h | 26 InstructionTemplate(const Instruction *Instr);
39 const Instruction &getInstr() const { return *Instr; }
53 const Instruction *Instr;
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| ParallelSnippetGenerator.cpp | 83 getVariablesWithTiedOperands(const Instruction &Instr) {
85 for (const auto &Var : Instr.Variables)
160 const Instruction &Instr = Variant.getInstr();
163 Instr.hasMemoryOperands()
167 const AliasingConfigurations SelfAliasing(Instr, Instr);
180 const auto TiedVariables = getVariablesWithTiedOperands(Instr);
190 for (const auto &Op : Instr.Operands) {
203 for (const auto &Op : Instr.Operands) {
|
| /src/external/apache2/llvm/dist/llvm/utils/TableGen/GlobalISel/ |
| GIMatchDagPredicate.cpp | 27 GIMatchDagContext &Ctx, StringRef Name, const CodeGenInstruction &Instr)
30 Instr(Instr) {}
33 OS << "$mi.getOpcode() == " << Instr.TheDef->getName();
44 for (const CodeGenInstruction *Instr : Instrs) {
45 OS << Separator << Instr->TheDef->getName();
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| GIMatchDagPredicate.h | 80 const CodeGenInstruction &Instr;
84 const CodeGenInstruction &Instr);
90 const CodeGenInstruction *getInstr() const { return &Instr; }
105 void addOpcode(const CodeGenInstruction *Instr) { Instrs.push_back(Instr); }
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/WebAssembly/ |
| WebAssemblyDebugValueManager.cpp | 22 MachineInstr *Instr) {
23 const auto *MF = Instr->getParent()->getParent();
28 if (!Instr->getOperand(0).isReg())
30 CurrentReg = Instr->getOperand(0).getReg();
33 MachineBasicBlock::iterator DI = *Instr;
35 for (MachineBasicBlock::iterator DE = Instr->getParent()->end(); DI != DE;
38 DI->hasDebugOperandForReg(Instr->getOperand(0).getReg()))
|
| WebAssemblyDebugValueManager.h | 29 WebAssemblyDebugValueManager(MachineInstr *Instr);
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/Lanai/Disassembler/ |
| LanaiDisassembler.h | 30 getInstruction(MCInst &Instr, uint64_t &Size, ArrayRef<uint8_t> Bytes,
|
| LanaiDisassembler.cpp | 90 static void PostOperandDecodeAdjust(MCInst &Instr, uint32_t Insn) {
94 if (isRMOpcode(Instr.getOpcode()))
96 else if (isSPLSOpcode(Instr.getOpcode()))
98 else if (isRRMOpcode(Instr.getOpcode())) {
112 if (Instr.getOperand(2).isReg()) {
113 Instr.getOperand(2).setReg(Lanai::R0);
115 if (Instr.getOperand(2).isImm())
116 Instr.getOperand(2).setImm(0);
127 Instr.addOperand(MCOperand::createImm(AluOp));
132 LanaiDisassembler::getInstruction(MCInst &Instr, uint64_t &Size
[all...] |
| /src/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/ |
| DbgEntityHistoryCalculator.h | 79 Entry(const MachineInstr *Instr, EntryKind Kind)
80 : Instr(Instr, Kind), EndIndex(NoEntry) {}
82 const MachineInstr *getInstr() const { return Instr.getPointer(); }
84 EntryKind getEntryKind() const { return Instr.getInt(); }
93 PointerIntPair<const MachineInstr *, 1, EntryKind> Instr;
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/Disassembler/ |
| AArch64Disassembler.h | 27 getInstruction(MCInst &Instr, uint64_t &Size, ArrayRef<uint8_t> Bytes,
|
| /src/external/apache2/llvm/dist/llvm/tools/llvm-exegesis/lib/X86/ |
| Target.cpp | 58 static const char *isInvalidMemoryInstr(const Instruction &Instr) {
59 switch (Instr.Description.TSFlags & X86II::FormMask) {
158 return (Instr.Description.Opcode == X86::POP16r ||
159 Instr.Description.Opcode == X86::POP32r ||
160 Instr.Description.Opcode == X86::PUSH16r ||
161 Instr.Description.Opcode == X86::PUSH32r)
193 static const char *isInvalidOpcode(const Instruction &Instr) {
194 const auto OpcodeName = Instr.Name;
195 if ((Instr.Description.TSFlags & X86II::FormMask) == X86II::Pseudo)
201 switch (Instr.Description.Opcode)
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/ |
| R600OptimizeVectorRegisters.cpp | 51 MachineInstr *Instr;
55 RegSeqInfo(MachineRegisterInfo &MRI, MachineInstr *MI) : Instr(MI) {
57 for (unsigned i = 1, e = Instr->getNumOperands(); i < e; i+=2) {
58 MachineOperand &MO = Instr->getOperand(i);
59 unsigned Chan = Instr->getOperand(i + 1).getImm();
70 return RSI.Instr == Instr;
185 Register Reg = RSI->Instr->getOperand(0).getReg();
186 MachineBasicBlock::iterator Pos = RSI->Instr;
190 Register SrcVec = BaseRSI->Instr->getOperand(0).getReg()
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/M68k/Disassembler/ |
| M68kDisassembler.cpp | 126 DecodeStatus getInstruction(MCInst &Instr, uint64_t &Size,
129 void decodeReg(MCInst &Instr, unsigned int Bead,
131 void decodeImm(MCInst &Instr, unsigned int Bead,
133 unsigned int getRegOperandIndex(MCInst &Instr, unsigned int Bead) const;
134 unsigned int getImmOperandIndex(MCInst &Instr, unsigned int Bead) const;
371 unsigned M68kDisassembler::getRegOperandIndex(MCInst &Instr,
375 const MCInstrDesc &Desc = MCII->get(Instr.getOpcode());
376 auto MIOpIdx = M68k::getLogicalOperandIdx(Instr.getOpcode(), Ext & 7);
378 if (M68kII::hasMultiMIOperands(Instr.getOpcode(), Ext & 7)) {
391 unsigned M68kDisassembler::getImmOperandIndex(MCInst &Instr,
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/BPF/Disassembler/ |
| BPFDisassembler.cpp | 68 DecodeStatus getInstruction(MCInst &Instr, uint64_t &Size,
164 DecodeStatus BPFDisassembler::getInstruction(MCInst &Instr, uint64_t &Size,
181 Result = decodeInstruction(DecoderTableBPFALU3264, Instr, Insn, Address,
184 Result = decodeInstruction(DecoderTableBPF64, Instr, Insn, Address, this,
189 switch (Instr.getOpcode()) {
201 auto& Op = Instr.getOperand(1);
211 auto Op = Instr.getOperand(0);
212 Instr.clear();
213 Instr.addOperand(MCOperand::createReg(BPF::R6));
214 Instr.addOperand(Op)
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Transforms/Scalar/ |
| CorrelatedValuePropagation.cpp | 672 static bool narrowSDivOrSRem(BinaryOperator *Instr, LazyValueInfo *LVI) {
673 assert(Instr->getOpcode() == Instruction::SDiv ||
674 Instr->getOpcode() == Instruction::SRem);
675 if (Instr->getType()->isVectorTy())
678 // Find the smallest power of two bitwidth that's sufficient to hold Instr's
680 unsigned OrigWidth = Instr->getType()->getIntegerBitWidth();
686 for (auto I : zip(Instr->operands(), CRs)) {
687 std::get<1>(I) = LVI->getConstantRange(std::get<0>(I), Instr);
707 IRBuilder<> B{Instr};
708 auto *TruncTy = Type::getIntNTy(Instr->getContext(), NewWidth)
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/NVPTX/ |
| NVPTXProxyRegErasure.cpp | 56 void replaceRegisterUsage(MachineInstr &Instr, MachineOperand &From,
109 void NVPTXProxyRegErasure::replaceRegisterUsage(MachineInstr &Instr,
112 for (auto &Op : Instr.uses()) {
|
| /src/external/apache2/llvm/dist/llvm/lib/IR/ |
| ReplaceConstant.cpp | 22 Instruction *createReplacementInstr(ConstantExpr *CE, Instruction *Instr) {
23 IRBuilder<NoFolder> Builder(Instr);
|
