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  /src/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/
ExecutionDomainFix.h 66 SmallVector<MachineInstr *, 8> Instrs;
72 bool isCollapsed() const { return Instrs.empty(); }
112 Instrs.clear();
  /src/external/apache2/llvm/dist/llvm/utils/TableGen/GlobalISel/
GIMatchDagPredicate.h 100 SmallVector<const CodeGenInstruction *, 4> Instrs;
105 void addOpcode(const CodeGenInstruction *Instr) { Instrs.push_back(Instr); }
112 return Instrs;
GIMatchDagPredicate.cpp 44 for (const CodeGenInstruction *Instr : Instrs) {
  /src/external/apache2/llvm/dist/llvm/lib/Target/ARM/MCTargetDesc/
ARMAsmBackendDarwin.h 36 ArrayRef<MCCFIInstruction> Instrs) const override;
ARMAsmBackend.cpp 1109 ArrayRef<MCCFIInstruction> Instrs) const {
1115 if (Instrs.empty())
1124 for (size_t i = 0, e = Instrs.size(); i != e; ++i) {
1126 const MCCFIInstruction &Inst = Instrs[i];
  /src/external/apache2/llvm/dist/llvm/lib/CodeGen/
ExecutionDomainFix.cpp 116 while (!dv->Instrs.empty())
117 TII->setExecutionDomain(*dv->Instrs.pop_back_val(), domain);
137 A->Instrs.append(B->Instrs.begin(), B->Instrs.end());
379 dv->Instrs.push_back(mi);
MachineTraceMetrics.cpp 1214 unsigned Instrs = TBI.InstrDepth;
1217 Instrs += TE.MTM.BlockInfo[getBlockNum()].InstrCount;
1219 Instrs /= IW;
1221 return std::max(Instrs, PRMax);
1234 auto extraCycles = [this](ArrayRef<const MCSchedClassDesc *> Instrs,
1238 for (const MCSchedClassDesc *SC : Instrs) {
1265 // Instrs: #instructions in current trace outside current block.
1266 unsigned Instrs = TBI.InstrDepth + TBI.InstrHeight;
1269 Instrs += TE.MTM.getResources(MBB)->InstrCount;
1270 Instrs += ExtraInstrs.size()
    [all...]
MachineCombiner.cpp 116 void instr2instrSC(SmallVectorImpl<MachineInstr *> &Instrs,
298 assert(!InsInstrs.empty() && "Only support sequences that insert instrs.");
390 SmallVectorImpl<MachineInstr *> &Instrs,
392 for (auto *InstrPtr : Instrs) {
CFIInstrInserter.cpp 184 const std::vector<MCCFIInstruction> &Instrs = MF->getFrameInstructions();
195 const MCCFIInstruction &CFI = Instrs[CFIIndex];
MachineOutliner.cpp 649 const std::vector<MCCFIInstruction> &Instrs =
658 MCCFIInstruction CFI = Instrs[CFIIndex];
  /src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/MCTargetDesc/
AArch64AsmBackend.cpp 562 ArrayRef<MCCFIInstruction> Instrs) const override {
563 if (Instrs.empty())
571 for (size_t i = 0, e = Instrs.size(); i != e; ++i) {
572 const MCCFIInstruction &Inst = Instrs[i];
593 const MCCFIInstruction &LRPush = Instrs[++i];
596 const MCCFIInstruction &FPPush = Instrs[++i];
633 const MCCFIInstruction &Inst2 = Instrs[++i];
  /src/external/apache2/llvm/dist/llvm/lib/Transforms/Vectorize/
LoadStoreVectorizer.cpp 177 bool vectorizeInstructions(ArrayRef<Instruction *> Instrs);
615 SmallVector<Instruction *, 16> Instrs;
619 Instrs.push_back(I);
621 Instrs.push_back(GEP);
625 for (Instruction *I : Instrs)
920 bool Vectorizer::vectorizeInstructions(ArrayRef<Instruction *> Instrs) {
921 LLVM_DEBUG(dbgs() << "LSV: Vectorizing " << Instrs.size()
928 for (int i = 0, e = Instrs.size(); i < e; ++i) {
934 if (isConsecutiveAccess(Instrs[i], Instrs[j]))
    [all...]
  /src/external/apache2/llvm/dist/llvm/utils/TableGen/
AsmWriterEmitter.cpp 240 std::string Instrs = InstrsForCase[i];
241 if (Instrs.size() > 70) {
242 Instrs.erase(Instrs.begin()+70, Instrs.end());
243 Instrs += "...";
246 if (!Instrs.empty())
247 UniqueOperandCommands[i] = " // " + Instrs + "\n" +
CodeGenDAGPatterns.cpp 3674 getInstructionsInTree(TreePatternNode *Tree, SmallVectorImpl<Record*> &Instrs) {
3678 Instrs.push_back(Tree->getOperator());
3680 getInstructionsInTree(Tree->getChild(i), Instrs);
3885 std::vector<Record*> Instrs = Records.getAllDerivedDefinitions("Instruction");
3887 for (Record *Instr : Instrs) {
4075 SmallVector<Record*, 8> Instrs;
4076 getInstructionsInTree(PTM.getDstPattern(), Instrs);
4077 if (Instrs.empty())
4084 for (const Record *Instr : Instrs) {
4119 (Instrs.size() == 1
    [all...]
  /src/external/apache2/llvm/dist/llvm/lib/MC/
MCWin64EH.cpp 527 const auto &Instrs = InstrsIter->second;
529 if (Instrs.size() != EpilogInstrs.size())
533 for (unsigned i = 0; i < Instrs.size(); ++i)
534 if (Instrs[i].Operation != EpilogInstrs[i].Operation ||
535 Instrs[i].Offset != EpilogInstrs[i].Offset ||
536 Instrs[i].Register != EpilogInstrs[i].Register) {
  /src/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/MCTargetDesc/
HexagonMCCodeEmitter.cpp 471 auto Instrs = HexagonMCInstrInfo::bundleInstructions(*State.Bundle);
472 for (auto I = Instrs.begin(), N = Instrs.end(); I != N; ++I) {
735 auto Instrs = HexagonMCInstrInfo::bundleInstructions(*State.Bundle);
736 const MCOperand *I = Instrs.begin() + State.Index - 1;
739 assert(I != Instrs.begin() - 1 && "Couldn't find producer");
  /src/external/apache2/llvm/dist/llvm/lib/Target/ARM/
ARMLoadStoreOptimizer.cpp 145 SmallVector<MachineInstr*, 4> Instrs;
147 /// Index in Instrs of the instruction being latest in the schedule.
150 /// Index in Instrs of the instruction being earliest in the schedule.
179 ArrayRef<MachineInstr*> Instrs);
185 ArrayRef<MachineInstr*> Instrs) const;
630 ArrayRef<MachineInstr*> Instrs) {
827 MIB.cloneMergedMemRefs(Instrs);
837 ArrayRef<MachineInstr*> Instrs) const {
853 MIB.cloneMergedMemRefs(Instrs);
859 const MachineInstr *First = Cand.Instrs.front()
    [all...]
  /src/external/apache2/llvm/dist/clang/lib/Analysis/
ThreadSafetyTIL.cpp 155 for (auto *Instr : Instrs)
  /src/external/apache2/llvm/dist/llvm/lib/Target/X86/
X86DomainReassignment.cpp 304 SmallVector<MachineInstr *, 8> Instrs;
341 Instrs.push_back(I);
345 return Instrs;
358 for (MachineInstr *MI : Instrs) {
  /src/external/apache2/llvm/dist/clang/include/clang/Analysis/Analyses/
ThreadSafetyTIL.h 1537 Args(std::move(As)), Instrs(std::move(Is)), TermInstr(T) {}
1557 InstrArray &instructions() { return Instrs; }
1558 const InstrArray &instructions() const { return Instrs; }
1590 Instrs.reserveCheck(1, Arena);
1591 Instrs.push_back(V);
1602 void reserveInstructions(unsigned Nins) { Instrs.reserve(Nins, Arena); }
1616 typename V::template Container<SExpr*> Nis(Vs, Instrs.size());
1625 for (const auto *E : Instrs) {
1673 InstrArray Instrs;
  /src/external/apache2/llvm/dist/llvm/lib/Target/X86/MCTargetDesc/
X86AsmBackend.cpp 1440 generateCompactUnwindEncoding(ArrayRef<MCCFIInstruction> Instrs) const override {
1441 if (Instrs.empty()) return 0;
1459 for (unsigned i = 0, e = Instrs.size(); i != e; ++i) {
1460 const MCCFIInstruction &Inst = Instrs[i];
  /src/external/apache2/llvm/dist/llvm/include/llvm/Analysis/
LoopAccessAnalysis.h 169 const SmallVectorImpl<Instruction *> &Instrs) const;
  /src/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/
HexagonGenInsert.cpp 1460 std::vector<MachineInstr*> Instrs;
1462 Instrs.push_back(&*I);
1464 for (auto I = Instrs.begin(), E = Instrs.end(); I != E; ++I) {
  /src/external/apache2/llvm/dist/llvm/lib/Analysis/
ModuleSummaryAnalysis.cpp 393 auto AddRefEdges = [&](const std::vector<const Instruction *> &Instrs,
396 for (const auto *I : Instrs) {
  /src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/
AArch64FrameLowering.cpp 3411 SmallVector<TagStoreInstr, 4> Instrs;
3412 Instrs.emplace_back(&MI, Offset, Size);
3429 Instrs.emplace_back(&MI, Offset, Size);
3449 MachineBasicBlock::iterator InsertI = Instrs.back().MI;
3452 llvm::stable_sort(Instrs,
3458 int64_t CurOffset = Instrs[0].Offset;
3459 for (auto &Instr : Instrs) {
3469 for (auto &Instr : Instrs) {

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