| /src/external/apache2/llvm/dist/llvm/lib/MCA/Stages/ |
| EntryStage.cpp | 11 /// purpose in life is to produce instructions for the rest of the pipeline.
38 Instructions.emplace_back(std::move(Inst));
61 auto Range = make_range(&Instructions[NumRetired], Instructions.end());
66 NumRetired = std::distance(Instructions.begin(), It);
67 // Erase instructions up to the first that hasn't been retired.
68 if ((NumRetired * 2) >= Instructions.size()) {
69 Instructions.erase(Instructions.begin(), It);
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| /src/external/apache2/llvm/dist/llvm/tools/llvm-exegesis/lib/ |
| SnippetRepetitor.cpp | 27 FillFunction Repeat(ArrayRef<MCInst> Instructions,
29 return [Instructions, MinInstructions](FunctionFiller &Filler) {
31 if (!Instructions.empty()) {
33 Entry.addInstructions(Instructions);
34 for (unsigned I = Instructions.size(); I < MinInstructions; ++I) {
35 Entry.addInstruction(Instructions[I % Instructions.size()]);
55 // Loop over the snippet ceil(MinInstructions / Instructions.Size()) times.
56 FillFunction Repeat(ArrayRef<MCInst> Instructions,
58 return [this, Instructions, MinInstructions](FunctionFiller &Filler)
[all...] |
| ParallelSnippetGenerator.cpp | 16 // instructions like x87.
18 // Ideally we would like the only limitation on executing instructions to be the
22 // To achieve that, one approach is to generate instructions that do not have
25 // For some instructions, this is trivial:
31 // four instructions two at a time on P23 and P0126.
33 // For some instructions, we just need to make sure that the source is
44 // Some instructions make this harder because they both read and write from
51 // number of instructions that can be issued in parallel.
54 // instructions will end up evenly distributed on {P0,P1,P5,P6}, but some CPUs
57 // instructions
[all...] |
| SnippetRepetitor.h | 39 // Returns a functor that repeats `Instructions` so that the function executes
40 // at least `MinInstructions` instructions.
41 virtual FillFunction Repeat(ArrayRef<MCInst> Instructions,
|
| BenchmarkResult.h | 37 std::vector<MCInst> Instructions;
67 const MCInst &keyInstruction() const { return Key.Instructions[0]; }
68 // The number of instructions inside the repeated snippet. For example, if a
69 // snippet of 3 instructions is repeated 4 times, this is 12.
|
| SnippetGenerator.cpp | 54 "Infeasible : target does not support memory instructions");
78 for (InstructionTemplate &IT : CT.Instructions) {
81 BC.Key.Instructions.push_back(IT.build());
86 computeRegisterInitialValues(CT.Instructions);
101 const std::vector<InstructionTemplate> &Instructions) const {
108 for (const InstructionTemplate &IT : Instructions) {
159 CT.Instructions.push_back(std::move(Variant));
171 CT.Instructions.push_back(std::move(Variant));
|
| Analysis.cpp | 135 assert(!Point.Key.Instructions.empty());
225 assert(!Point.Key.Instructions.empty());
226 // FIXME: we should be using the tuple of classes for instructions in the
253 const std::vector<MCInst> &Instructions,
255 if (Instructions.empty())
257 writeEscaped<kEscapeHtml>(OS, InstrInfo.getName(Instructions[0].getOpcode()));
258 if (Instructions.size() > 1)
259 OS << " (x" << Instructions.size() << ")";
265 const std::vector<MCInst> &Instructions,
268 for (const MCInst &Instr : Instructions) {
[all...] |
| SerialSnippetGenerator.cpp | 32 "Repeating two instructions"},
41 // Randomly iterate the set of instructions.
53 // Ignore instructions that we cannot run.
106 CT.Instructions.push_back(std::move(Variant));
128 CT.Instructions.push_back(std::move(Variant));
148 CT.Instructions.push_back(std::move(ThisIT));
149 CT.Instructions.push_back(std::move(OtherIT));
|
| BenchmarkRunner.cpp | 147 const std::vector<MCInst> &Instructions = BC.Key.Instructions;
168 // Assemble at least kMinInstructionsForSnippet instructions by repeating
170 // understands that the inside instructions are repeated.
178 Repetitor->Repeat(Instructions, kMinInstructionsForSnippet),
188 // Assemble NumRepetitions instructions repetitions of the snippet for
191 Repetitor->Repeat(Instructions, InstrBenchmark.NumRepetitions);
228 BM.PerSnippetValue *= static_cast<double>(Instructions.size()) /
|
| /src/external/apache2/llvm/dist/llvm/tools/llvm-exegesis/lib/Mips/ |
| Target.cpp | 71 // Generates instructions to load an immediate value into a register.
95 std::vector<MCInst> Instructions;
101 Instructions.push_back(
106 Instructions.push_back(
112 Instructions.push_back(
120 Instructions.push_back(
127 return Instructions;
|
| /src/external/apache2/llvm/dist/llvm/utils/TableGen/ |
| CodeGenTarget.h | 52 std::unique_ptr<CodeGenInstruction>> Instructions;
147 if (Instructions.empty()) ReadInstructions();
148 return Instructions;
153 if (Instructions.empty()) ReadInstructions();
154 auto I = Instructions.find(InstRec);
155 assert(I != Instructions.end() && "Not an instruction");
159 /// Returns the number of predefined instructions.
162 /// Returns the number of pseudo instructions.
169 /// Return all of the instructions defined by the target, ordered by their
171 /// The following order of instructions is also guaranteed
[all...] |
| /src/external/apache2/llvm/dist/llvm/include/llvm/MCA/Stages/ |
| EntryStage.h | 11 /// purpose in life is to pick instructions in sequence and move them to the
28 SmallVector<std::unique_ptr<Instruction>, 16> Instructions;
|
| /src/external/apache2/llvm/dist/llvm/tools/llvm-mca/ |
| CodeRegion.h | 51 /// It identifies a sequence of machine instructions.
55 // Instructions that form this region.
56 llvm::SmallVector<llvm::MCInst, 8> Instructions;
69 Instructions.emplace_back(Instruction);
76 bool empty() const { return Instructions.empty(); }
79 llvm::ArrayRef<llvm::MCInst> getInstructions() const { return Instructions; }
|
| /src/external/apache2/llvm/dist/llvm/lib/Analysis/ |
| StackLifetime.cpp | 20 #include "llvm/IR/Instructions.h"
57 auto It = std::upper_bound(Instructions.begin() + ItBB->getSecond().first + 1,
58 Instructions.begin() + ItBB->getSecond().second, I,
63 unsigned InstNum = It - Instructions.begin();
120 // Compute instruction numbering. Only the following instructions are
127 LLVM_DEBUG(dbgs() << "Instructions:\n");
129 LLVM_DEBUG(dbgs() << " " << Instructions.size() << ": BB " << BB->getName()
131 auto BBStart = Instructions.size();
132 Instructions.push_back(nullptr);
139 BlockInstRange[BB] = std::make_pair(BBStart, Instructions.size())
[all...] |
| /src/external/apache2/llvm/dist/llvm/tools/llvm-mca/Views/ |
| SummaryView.cpp | 45 // the retire stage for instructions that are part of iteration #0.
88 DV.Instructions = Source.size();
89 DV.Iterations = (LastInstructionIdx / DV.Instructions) + 1;
90 DV.TotalInstructions = DV.Instructions * DV.Iterations;
104 {"Instructions", DV.TotalInstructions},
|
| SummaryView.h | 17 /// Instructions: 900
24 /// performance indicators are 'Total Cycles' and IPC (Instructions Per Cycle).
46 // The total number of micro opcodes contributed by a block of instructions.
50 unsigned Instructions;
|
| /src/external/apache2/llvm/dist/llvm/include/llvm/MC/ |
| MCWinEH.h | 31 // Check whether two instructions refer to the same operation
56 std::vector<Instruction> Instructions;
68 if (!Instructions.empty())
|
| /src/external/apache2/llvm/dist/llvm/include/llvm/DebugInfo/DWARF/ |
| DWARFDebugFrame.h | 33 /// instructions and put into an UnwindRow.
226 /// row represents the initial instructions for a CIE. If the address has a
238 /// The address will be valid when parsing the instructions in a FDE. If
239 /// invalid, this object represents the initial instructions of a CIE.
383 /// Represent a sequence of Call Frame Information instructions that, when read
415 iterator begin() { return Instructions.begin(); }
416 const_iterator begin() const { return Instructions.begin(); }
417 iterator end() { return Instructions.end(); }
418 const_iterator end() const { return Instructions.end(); }
420 unsigned size() const { return (unsigned)Instructions.size();
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/MC/ |
| MCWin64EH.cpp | 183 uint8_t numCodes = CountOfUnwindCodes(info->Instructions);
188 WinEH::Instruction &frameInst = info->Instructions[info->LastFrameInst];
194 // Emit unwind instructions (in reverse order).
195 uint8_t numInst = info->Instructions.size();
197 WinEH::Instruction inst = info->Instructions.back();
198 info->Instructions.pop_back();
547 static void simplifyOpcodes(std::vector<WinEH::Instruction> &Instructions,
597 // Iterate over instructions in a forward order (for prologues),
601 for (auto It = Instructions.rbegin(); It != Instructions.rend(); It++
[all...] |
| MCStreamer.cpp | 126 (MAB ? MAB->generateCompactUnwindEncoding(FI.Instructions) : 0);
485 CurFrame->Instructions.push_back(Instruction);
496 CurFrame->Instructions.push_back(Instruction);
506 CurFrame->Instructions.push_back(Instruction);
516 CurFrame->Instructions.push_back(Instruction);
527 CurFrame->Instructions.push_back(Instruction);
537 CurFrame->Instructions.push_back(Instruction);
563 CurFrame->Instructions.push_back(Instruction);
573 CurFrame->Instructions.push_back(Instruction);
583 CurFrame->Instructions.push_back(Instruction)
[all...] |
| /src/external/apache2/llvm/dist/llvm/tools/llvm-cfi-verify/lib/ |
| FileAnalysis.cpp | 52 "will result in false positives for 'CFI unprotected' instructions."),
124 Instructions.find(InstrMeta.VMAddress);
125 if (KV == Instructions.end() || KV == Instructions.begin())
137 Instructions.find(InstrMeta.VMAddress);
138 if (KV == Instructions.end() || ++KV == Instructions.end())
156 const auto &InstrKV = Instructions.find(Address);
157 if (InstrKV == Instructions.end())
164 const auto &InstrKV = Instructions.find(Address)
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/X86/MCTargetDesc/ |
| X86WinCOFFTargetStreamer.cpp | 63 SmallVector<FPOInstruction, 5> Instructions;
186 // Complain if there were prologue setup instructions but no end prologue.
187 if (!CurFPOData->Instructions.empty()) {
189 CurFPOData->Instructions.clear();
210 CurFPOData->Instructions.push_back(Inst);
221 CurFPOData->Instructions.push_back(Inst);
232 CurFPOData->Instructions.push_back(Inst);
239 if (!llvm::any_of(CurFPOData->Instructions, [](const FPOInstruction &Inst) {
250 CurFPOData->Instructions.push_back(Inst);
414 for (const FPOInstruction &Inst : FPO->Instructions) {
[all...] |
| /src/external/apache2/llvm/dist/llvm/include/llvm/Analysis/ |
| StackLifetime.h | 31 /// Live ranges are represented as sets of "interesting" instructions, which are
32 /// defined as instructions that may start or end an alloca's lifetime. These
36 /// Interesting instructions are numbered in the depth-first walk of the CFG,
62 /// This class represents a set of interesting instructions where an alloca is
97 /// Interesting instructions. Instructions of the same block are adjustent
99 SmallVector<const IntrinsicInst *, 64> Instructions;
102 /// Instructions inside each BB have monotonic and consecutive ids.
147 return make_filter_range(Instructions, NotNull);
150 /// Returns a set of "interesting" instructions where the given alloca i
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Transforms/Scalar/ |
| AnnotationRemarks.cpp | 9 // Generate remarks for instructions marked with !annotation.
19 #include "llvm/IR/Instructions.h"
33 static void tryEmitAutoInitRemark(ArrayRef<Instruction *> Instructions,
37 for (Instruction *I : Instructions) {
84 // Track all annotated instructions aggregated based on their debug location.
88 // First, generate a summary of the annotated instructions.
90 for (Instruction &I : instructions(F)) {
106 << "Annotated " << NV("count", KV.second) << " instructions with "
109 // For each debug location, look for all the instructions with annotations and
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/Mips/ |
| MipsInstructionSelector.cpp | 236 assert(STI.hasMSA() && "Vector instructions require target with MSA.");
755 SmallVector<struct Instr, 2> Instructions;
765 Instructions.emplace_back(Mips::XOR, Temp, LHS, RHS);
766 Instructions.emplace_back(Mips::SLTiu, ICMPReg, Temp, 1);
769 Instructions.emplace_back(Mips::XOR, Temp, LHS, RHS);
770 Instructions.emplace_back(Mips::SLTu, ICMPReg, Mips::ZERO, Temp);
773 Instructions.emplace_back(Mips::SLTu, ICMPReg, RHS, LHS);
776 Instructions.emplace_back(Mips::SLTu, Temp, LHS, RHS);
777 Instructions.emplace_back(Mips::XORi, ICMPReg, Temp, 1);
780 Instructions.emplace_back(Mips::SLTu, ICMPReg, LHS, RHS)
[all...] |
