| /src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/GISel/ |
| AArch64GlobalISelUtils.cpp | 154 AArch64CC::CondCode &CondCode2, bool &Invert) {
155 Invert = false;
162 Invert = true;
175 Invert = true;
|
| AArch64GlobalISelUtils.h | 72 /// \param [out] Invert - True if the comparison must be inverted with a NOT.
76 bool &Invert);
|
| AArch64PostLegalizerLowering.cpp | 930 bool Invert;
932 changeVectorFCMPPredToAArch64CC(Pred, CC, CC2, Invert);
947 if (Invert)
|
| AArch64InstructionSelector.cpp | 125 bool tryOptAndIntoCompareBranch(MachineInstr &AndInst, bool Invert,
1068 bool Invert) {
1083 if (Invert) {
1100 if (Invert) {
1119 if (Invert) {
1204 Optimized |= TryFoldBinOpIntoSelect(False, True, /*Invert = */ false);
1205 Optimized |= TryFoldBinOpIntoSelect(True, False, /*Invert = */ true);
1240 static Register getTestBitReg(Register Reg, uint64_t &Bit, bool &Invert,
1349 Invert = !Invert;
[all...] |
| /src/external/lgpl3/gmp/dist/mpn/powerpc64/mode64/p8/ |
| invert_limb.asm | 1 dnl PowerPC-64 mpn_invert_limb -- Invert a normalized limb.
|
| /src/external/lgpl3/gmp/dist/mpn/alpha/ |
| invert_limb.asm | 1 dnl Alpha mpn_invert_limb -- Invert a normalized limb.
|
| /src/external/lgpl3/gmp/dist/mpn/arm64/ |
| invert_limb.asm | 1 dnl ARM64 mpn_invert_limb -- Invert a normalized limb.
|
| /src/external/lgpl3/gmp/dist/mpn/ia64/ |
| invert_limb.asm | 1 dnl IA-64 mpn_invert_limb -- Invert a normalized limb.
|
| /src/external/lgpl3/gmp/dist/mpn/powerpc64/mode64/ |
| invert_limb.asm | 1 dnl PowerPC-64 mpn_invert_limb -- Invert a normalized limb.
|
| /src/external/lgpl3/gmp/dist/mpn/x86_64/ |
| invert_limb.asm | 1 dnl AMD64 mpn_invert_limb -- Invert a normalized limb.
|
| /src/external/apache2/llvm/dist/llvm/lib/Transforms/Scalar/ |
| StructurizeCFG.cpp | 271 Value *buildCondition(BranchInst *Term, unsigned Idx, bool Invert);
446 bool Invert) {
447 Value *Cond = Invert ? BoolFalse : BoolTrue;
451 if (Idx != (unsigned)Invert)
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/SystemZ/ |
| SystemZISelLowering.h | 674 bool Invert) const;
682 bool Invert = false) const;
|
| SystemZISelLowering.cpp | 2763 // or 0 if neither can be done directly. Indicate in Invert whether the
2766 bool &Invert) {
2768 Invert = false;
2774 Invert = true;
2849 bool Invert = false;
2854 Invert = true;
2871 Invert = true;
2890 if (unsigned Opcode = getVectorComparisonOrInvert(CC, Mode, Invert))
2894 if (unsigned Opcode = getVectorComparisonOrInvert(CC, Mode, Invert))
2903 if (Invert) {
[all...] |
| /src/external/lgpl3/gmp/dist/mpn/arm/ |
| invert_limb.asm | 1 dnl ARM mpn_invert_limb -- Invert a normalized limb.
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/Lanai/ |
| LanaiInstrInfo.cpp | 499 bool Invert = !DefMI;
506 MachineOperand FalseReg = MI.getOperand(Invert ? 1 : 2);
523 if (Invert)
|
| LanaiISelLowering.cpp | 1341 // * Invert is set when N is the all zero/ones constant when CC is false.
1345 // * X = 0, Invert = False and OtherOp = Y
1346 // * Y = 0, Invert = True and OtherOp = X
1348 bool &Invert, SDValue &OtherOp,
1358 Invert = false;
1363 Invert = true;
1379 Invert = true;
1388 Invert = !AllOnes;
|
| /src/external/lgpl3/gmp/dist/mpn/powerpc32/ |
| invert_limb.asm | 1 dnl PowerPC-32 mpn_invert_limb -- Invert a normalized limb.
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/MSP430/ |
| MSP430ISelLowering.cpp | 1168 bool Invert = false;
1180 Invert = true;
1188 Invert = true;
1206 if (Invert)
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/ |
| AArch64ISelDAGToDAG.cpp | 189 template <MVT::SimpleValueType VT, bool Invert = false>
191 return SelectSVELogicalImm(N, VT, Imm, Invert);
329 bool SelectSVELogicalImm(SDValue N, MVT VT, SDValue &Imm, bool Invert);
3188 bool Invert) {
3193 if (Invert)
|
| AArch64ISelLowering.cpp | 2347 bool &Invert) {
2348 Invert = false;
2355 Invert = true;
2368 Invert = true;
3039 // If the operand is an overflow checking operation, invert the condition
3043 // (csel 1, 0, invert(cc), overflow_op_bool)
3167 // CSINC Wd, WZR, WZR, invert(cond).
15286 static SDValue getTestBitOperand(SDValue Op, unsigned &Bit, bool &Invert,
15300 return getTestBitOperand(Op->getOperand(0), Bit, Invert, DAG);
15306 return getTestBitOperand(Op->getOperand(0), Bit, Invert, DAG)
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Transforms/Utils/ |
| SimplifyCFG.cpp | 2368 bool Invert = false;
2371 Invert = true;
2373 assert(EndBB == BI->getSuccessor(!Invert) && "No edge from to end block");
2467 if (Invert)
2514 if (Invert)
3078 // If we need to invert the condition in the pred block to match, do so now.
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/PowerPC/ |
| PPCISelDAGToDAG.cpp | 2717 // ZExtInvert - invert the condition code, zero-extend value
2719 // SExtInvert - invert the condition code, sign-extend value
4144 static unsigned getCRIdxForSetCC(ISD::CondCode CC, bool &Invert) {
4145 Invert = false;
4156 case ISD::SETGE: Invert = true; return 0; // !Bit #0 = SETUGE
4158 case ISD::SETLE: Invert = true; return 1; // !Bit #1 = SETULE
4160 case ISD::SETNE: Invert = true; return 2; // !Bit #2 = SETUNE
4161 case ISD::SETO: Invert = true; return 3; // !Bit #3 = SETO
5535 // the mask elements (reverse and invert them).
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/ARM/ |
| ARMISelLowering.cpp | 4069 // Invert the bits.
6429 bool Invert = false;
6489 Invert = true; LLVM_FALLTHROUGH;
6502 case ISD::SETULE: Invert = true; Opc = ARMCC::GT; break;
6504 case ISD::SETULT: Invert = true; Opc = ARMCC::GE; break;
6505 case ISD::SETUEQ: Invert = true; LLVM_FALLTHROUGH;
6513 if (Invert)
6517 case ISD::SETUO: Invert = true; LLVM_FALLTHROUGH;
6525 if (Invert)
6538 Invert = true; LLVM_FALLTHROUGH
[all...] |
| ARMBaseInstrInfo.cpp | 2260 // After swapping the MOVCC operands, also invert the condition.
2336 bool Invert = !DefMI;
2343 MachineOperand FalseReg = MI.getOperand(Invert ? 2 : 1);
2361 if (Invert)
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/M68k/ |
| M68kISelLowering.cpp | 1932 bool Invert = (CC == ISD::SETNE) ^ isNullConstant(Op1);
1933 if (!Invert)
|
