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    Searched refs:IsAGPR (Results 1 - 6 of 6) sorted by relevancy

  /src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/
AMDGPUAsmPrinter.cpp 809 bool IsAGPR = false;
895 IsAGPR = true;
907 IsAGPR = true;
917 IsAGPR = true;
929 IsAGPR = true;
939 IsAGPR = true;
949 IsAGPR = true;
961 IsAGPR = true;
973 IsAGPR = true;
983 IsAGPR = true
    [all...]
SIFixSGPRCopies.cpp 262 bool IsAGPR = TRI->hasAGPRs(DstRC);
281 if (IsAGPR) {
790 TRI->isAGPR(*MRI, UseMI->getOperand(0).getReg())) ||
791 TRI->isAGPR(*MRI, Use.getReg());
SIRegisterInfo.cpp 1043 const bool IsAGPR = !ST.hasGFX90AInsts() && hasAGPRs(RC);
1048 unsigned EltSize = (IsFlat && !IsAGPR) ? std::min(RegWidth, 16u) : 4u;
1205 if (IsAGPR) {
1249 if (!IsAGPR && NeedSuperRegDef)
2249 bool SIRegisterInfo::isAGPR(const MachineRegisterInfo &MRI,
SILoadStoreOptimizer.cpp 924 bool IsAGPR = TRI->hasAGPRs(DataRC);
994 if (TRI->hasAGPRs(getDataRegClass(*MBBI)) != IsAGPR)
1002 if (IsAGPR && CI.InstClass == DS_WRITE)
SIInstrInfo.cpp 1729 !RI.isAGPR(MBB.getParent()->getRegInfo(), SrcOp.getReg())) {
2732 if (RI.isAGPR(*MRI, DstReg)) {
3808 const bool IsAGPR = !IsVGPR && RI.hasAGPRs(RC);
3809 if ((IsVGPR || IsAGPR) && MO.getSubReg()) {
4325 (RI.isAGPR(MRI, Dst->getReg()) != RI.isAGPR(MRI, Data->getReg()))) {
4331 (RI.isAGPR(MRI, Data->getReg()) != RI.isAGPR(MRI, Data2->getReg()))) {
4337 if ((Dst && RI.isAGPR(MRI, Dst->getReg())) ||
4338 (Data && RI.isAGPR(MRI, Data->getReg())) |
    [all...]
  /src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/Disassembler/
AMDGPUDisassembler.cpp 1245 bool IsAGPR = Val & 512;
1249 return createRegOperand(IsAGPR ? getAgprClassId(Width)

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