| /src/external/apache2/llvm/dist/llvm/utils/TableGen/GlobalISel/ |
| GIMatchDagOperands.h | 48 bool IsDef; 51 GIMatchDagOperand(unsigned Idx, StringRef Name, bool IsDef) 52 : Idx(Idx), Name(Name), IsDef(IsDef) {} 56 bool isDef() const { return IsDef; } 66 bool IsDef); 95 void add(StringRef Name, unsigned Idx, bool IsDef);
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| GIMatchDagOperands.cpp | 16 Profile(ID, Idx, Name, IsDef); 20 StringRef Name, bool IsDef) { 23 ID.AddBoolean(IsDef); 26 void GIMatchDagOperandList::add(StringRef Name, unsigned Idx, bool IsDef) { 28 Operands.emplace_back(Operands.size(), Name, IsDef); 35 I.value().isDef()); 46 if (I.isDef())
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| /src/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/ |
| MachineOperand.h | 91 /// IsDef - True if this is a def, false if this is a use of the register. 94 unsigned IsDef : 1; 288 /// isDef. Sometimes, if the operand is printed before '=', we don't print 372 return !IsDef; 375 bool isDef() const { 377 return IsDef; 387 return IsDeadOrKill & IsDef; 392 return IsDeadOrKill & !IsDef; 501 assert(isReg() && !IsDef && "Wrong MachineOperand mutator"); 507 assert(isReg() && IsDef && "Wrong MachineOperand mutator") [all...] |
| RDFGraph.h | 547 bool isDef() const { 793 static bool IsDef(const NodeAddr<NodeBase*> BA) {
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| /src/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/ |
| RDFDeadCode.cpp | 136 if (DFG.IsDef(RA)) 151 for (NodeAddr<DefNode*> DA : IA.Addr->members_if(DFG.IsDef, DFG)) 225 else if (DFG.IsDef(RA))
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| HexagonRDFOpt.cpp | 168 if (DFG.IsDef(RA) && DeadNodes.count(RA.Id)) 258 for (NodeAddr<DefNode*> DA : IA.Addr->members_if(DFG.IsDef, DFG)) {
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| HexagonConstExtenders.cpp | 327 bool IsDef = false; 502 if (ED.IsDef) 1163 ED.IsDef = true; 1183 ED.IsDef = true; 1188 ED.IsDef = true; 1192 ED.IsDef = true; 1274 if (!ED.IsDef) 1294 if (ED.IsDef) 1850 assert((!ED.IsDef || ED.Rd.Reg != 0) && "Missing Rd for def"); 1875 if (ED.IsDef && Diff != 0) [all...] |
| HexagonFrameLowering.h | 175 bool IsDef, bool IsKill) const;
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| RDFCopy.cpp | 144 for (NodeAddr<DefNode*> DA : SA.Addr->members_if(DFG.IsDef, DFG)) {
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| HexagonOptAddrMode.cpp | 183 if ((DFG->IsDef(AA) && AA.Id != OffsetRegRD) || 246 for (NodeAddr<DefNode *> DA : SA.Addr->members_if(DFG->IsDef, *DFG)) { 307 if ((DFG->IsDef(AA) && AA.Id != LRExtRegRD) ||
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| /src/external/apache2/llvm/dist/llvm/utils/TableGen/ |
| InstrDocsEmitter.cpp | 152 bool IsDef = i < II->Operands.NumDefs; 166 OS << "* " << (IsDef ? "DEF" : "USE") << " ``" << Op.Rec->getName() 177 OS << "* " << (IsDef ? "DEF" : "USE") << " ``" << Op.Rec->getName()
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| GlobalISelEmitter.cpp | 2765 bool IsDef; 2770 const Record *RegisterDef, bool IsDef = false) 2772 IsDef(IsDef), Target(Target) {} 2795 if (IsDef) 2811 bool IsDef; 2815 TempRegRenderer(unsigned InsnID, unsigned TempRegID, bool IsDef = false, 2819 SubRegIdx(SubReg), IsDef(IsDef), IsDead(IsDead) {} 2827 assert(!IsDef); [all...] |
| /src/external/apache2/llvm/dist/llvm/tools/llvm-exegesis/lib/ |
| MCInstrDescView.cpp | 44 bool Operand::isDef() const { return IsDef; } 46 bool Operand::isUse() const { return !IsDef; } 117 Operand.IsDef = (OpIndex < Description->getNumDefs()); 135 Operand.IsDef = true; 144 Operand.IsDef = false; 175 if (Op.isDef()) 179 if (Op.isDef() && Op.isImplicit()) 262 if (Op.isDef()) 330 if (Op.isReg() && Op.isDef() == SelectDef) [all...] |
| MCInstrDescView.h | 70 bool isDef() const; 86 bool IsDef = false;
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| Assembler.cpp | 102 const bool IsDef = OpIndex < MCID.getNumDefs(); 105 if (IsDef && !OpInfo.isOptionalDef())
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| /src/external/apache2/llvm/dist/llvm/lib/Target/Mips/ |
| MipsSEISelDAGToDAG.h | 32 void addDSPCtrlRegOperands(bool IsDef, MachineInstr &MI,
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| MipsDelaySlotFiller.cpp | 130 bool IsDef) const; 329 if (!MO.isReg() || !MO.isDef() || !(R = MO.getReg())) 419 if (checkRegDefsUses(NewDefs, NewUses, MO.getReg(), MO.isDef())) { 435 unsigned Reg, bool IsDef) const { 436 if (IsDef) {
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| MipsSEISelDAGToDAG.cpp | 52 void MipsSEDAGToDAGISel::addDSPCtrlRegOperands(bool IsDef, MachineInstr &MI, 57 IsDef ? RegState::ImplicitDefine : RegState::Implicit | RegState::Undef;
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| /src/external/apache2/llvm/dist/llvm/lib/CodeGen/ |
| MachineOperand.cpp | 94 if (isDef()) 104 if (IsDef == Val) 111 IsDef = Val; 115 IsDef = Val; 129 if (isDef()) 241 void MachineOperand::ChangeToRegister(Register Reg, bool isDef, bool isImp, 254 assert(!(isDead && !isDef) && "Dead flag on non-def"); 255 assert(!(isKill && isDef) && "Kill flag on def"); 259 IsDef = isDef; [all...] |
| RDFGraph.cpp | 611 if (Op.isDef() && Op.isDead()) 637 const MCPhysReg *ImpR = Op.isDef() ? D.getImplicitDefs() 1043 for (NodeAddr<DefNode*> DA : IA.Addr->members_if(IsDef, *this)) { 1089 for (NodeAddr<DefNode*> DA : IA.Addr->members_if(IsDef, *this)) { 1289 if (!Op.isReg() || !Op.isDef() || Op.isImplicit()) 1334 if (!Op.isReg() || !Op.isDef() || !Op.isImplicit()) 1398 for (NodeAddr<RefNode*> RA : IA.Addr->members_if(IsDef, *this)) 1549 if (RA.Addr->isDef()) 1645 return IsDef(RA) && (RA.Addr->getFlags() & NodeAttrs::Clobbering); 1648 return IsDef(RA) && !(RA.Addr->getFlags() & NodeAttrs::Clobbering) [all...] |
| BranchFolding.cpp | 1845 bool IsDef = false; 1856 IsDef = true; 1860 if (!IsDef) 1956 if (MO.isDef()) { 2019 if (!MO.isReg() || !MO.isDef() || MO.isDead())
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| RDFLiveness.cpp | 386 if (DFG.IsDef(R)) { 944 if (!Op.isReg() || !Op.isDef() || Op.isImplicit())
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| /src/external/apache2/llvm/dist/llvm/lib/Target/X86/ |
| X86LoadValueInjectionLoadHardening.cpp | 421 Owner.Addr->members_if(DataFlowGraph::IsDef, DFG)) { 474 NodeList Defs = ArgPhi.Addr->members_if(DataFlowGraph::IsDef, DFG); 486 NodeList Defs = SA.Addr->members_if(DataFlowGraph::IsDef, DFG);
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| /src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/ |
| AArch64LoadStoreOptimizer.cpp | 822 bool isDef = any_of(I.operands(), [DefReg, TRI](MachineOperand &MOP) { 823 return MOP.isReg() && MOP.isDef() && !MOP.isDebug() && MOP.getReg() && 826 if (!Fn(I, isDef)) 828 if (isDef) 884 [this, RegToRename, GetMatchingSubReg](MachineInstr &MI, bool IsDef) { 885 if (IsDef) { 891 (!SeenDef || (MOP.isDef() && MOP.isImplicit())) && 1401 bool IsDef) { 1414 FoundDef = IsDef; 1432 if (!MOP.isReg() || !MOP.isDef() || MOP.isDebug() || !MOP.getReg() | [all...] |
| /src/external/apache2/llvm/dist/llvm/lib/CodeGen/MIRParser/ |
| MIParser.cpp | 448 Optional<unsigned> &TiedDefIdx, bool IsDef = false); 964 if (parseRegisterOperand(MO, TiedDefIdx, /*IsDef=*/true)) 1175 return MO.isDef() ? "implicit-def" : "implicit"; 1469 if (!DefOperand.isReg() || !DefOperand.isDef()) 1493 bool IsDef) { 1494 unsigned Flags = IsDef ? RegState::Define : 0;
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