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    Searched refs:IsFSHL (Results 1 - 6 of 6) sorted by relevancy

  /src/external/apache2/llvm/dist/llvm/lib/CodeGen/GlobalISel/
LegalizerHelper.cpp 5416 const bool IsFSHL = MI.getOpcode() == TargetOpcode::G_FSHL;
5417 unsigned RevOpcode = IsFSHL ? TargetOpcode::G_FSHR : TargetOpcode::G_FSHL;
5428 if (IsFSHL) {
5454 const bool IsFSHL = MI.getOpcode() == TargetOpcode::G_FSHL;
5467 ShX = MIRBuilder.buildShl(Ty, X, IsFSHL ? ShAmt : InvShAmt).getReg(0);
5468 ShY = MIRBuilder.buildLShr(Ty, Y, IsFSHL ? InvShAmt : ShAmt).getReg(0);
5486 if (IsFSHL) {
5512 bool IsFSHL = MI.getOpcode() == TargetOpcode::G_FSHL;
5513 unsigned RevOpcode = IsFSHL ? TargetOpcode::G_FSHR : TargetOpcode::G_FSHL;
CombinerHelper.cpp 3897 bool IsFSHL = Opc == TargetOpcode::G_FSHL;
3899 MI.setDesc(Builder.getTII().get(IsFSHL ? TargetOpcode::G_ROTL
  /src/external/apache2/llvm/dist/llvm/lib/CodeGen/SelectionDAG/
TargetLowering.cpp 1683 bool IsFSHL = (Op.getOpcode() == ISD::FSHL);
1691 if (SimplifyDemandedBits(IsFSHL ? Op0 : Op1, DemandedBits, DemandedElts,
1699 APInt Demanded0 = DemandedBits.lshr(IsFSHL ? Amt : (BitWidth - Amt));
1700 APInt Demanded1 = DemandedBits << (IsFSHL ? (BitWidth - Amt) : Amt);
1708 Known2.One <<= (IsFSHL ? Amt : (BitWidth - Amt));
1709 Known2.Zero <<= (IsFSHL ? Amt : (BitWidth - Amt));
1710 Known.One.lshrInPlace(IsFSHL ? (BitWidth - Amt) : Amt);
1711 Known.Zero.lshrInPlace(IsFSHL ? (BitWidth - Amt) : Amt);
6474 bool IsFSHL = Node->getOpcode() == ISD::FSHL;
6480 unsigned RevOpcode = IsFSHL ? ISD::FSHR : ISD::FSHL
    [all...]
DAGCombiner.cpp 8945 bool IsFSHL = N->getOpcode() == ISD::FSHL;
8953 return IsFSHL ? N0 : N1;
8972 return IsFSHL ? N0 : N1;
8980 DAG.getConstant(IsFSHL ? BitWidth - ShAmt : ShAmt,
8984 DAG.getConstant(IsFSHL ? ShAmt : BitWidth - ShAmt,
9003 IsFSHL ? (((BitWidth - ShAmt) % BitWidth) / 8) : (ShAmt / 8);
9033 if (IsUndefOrZero(N0) && !IsFSHL && DAG.MaskedValueIsZero(N2, ~ModuloBits))
9035 if (IsUndefOrZero(N1) && IsFSHL && DAG.MaskedValueIsZero(N2, ~ModuloBits))
9043 unsigned RotOpc = IsFSHL ? ISD::ROTL : ISD::ROTR;
SelectionDAGBuilder.cpp 6402 bool IsFSHL = Intrinsic == Intrinsic::fshl;
6409 auto RotateOpcode = IsFSHL ? ISD::ROTL : ISD::ROTR;
6412 auto FunnelOpcode = IsFSHL ? ISD::FSHL : ISD::FSHR;
  /src/external/apache2/llvm/dist/llvm/lib/Target/PowerPC/
PPCISelLowering.cpp 8812 bool IsFSHL = Op.getOpcode() == ISD::FSHL;
8826 X = DAG.getNode(PPCISD::SHL, dl, VT, X, IsFSHL ? Z : SubZ);
8827 Y = DAG.getNode(PPCISD::SRL, dl, VT, Y, IsFSHL ? SubZ : Z);

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