| /src/external/apache2/llvm/dist/llvm/lib/Target/Mips/ |
| Mips16RegisterInfo.cpp | 123 bool IsKill = false;
139 IsKill = true;
141 MI.getOperand(OpNo).ChangeToRegister(FrameReg, false, false, IsKill);
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| MipsSERegisterInfo.cpp | 200 bool IsKill = false;
235 IsKill = true;
252 IsKill = true;
256 MI.getOperand(OpNo).ChangeToRegister(FrameReg, false, false, IsKill);
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| MipsSEFrameLowering.cpp | 193 .addReg(Src, getKillRegState(I->getOperand(0).isKill()));
235 unsigned SrcKill = getKillRegState(I->getOperand(0).isKill());
267 unsigned SrcKill = getKillRegState(I->getOperand(1).isKill());
326 TII.storeRegToStack(MBB, I, LoReg, I->getOperand(1).isKill(), FI, RC,
328 TII.storeRegToStack(MBB, I, HiReg, I->getOperand(2).isKill(), FI, RC,
390 TII.storeRegToStack(MBB, I, SrcReg, Op1.isKill(), FI, RC, &RegInfo, 0);
832 bool IsKill = !IsRAAndRetAddrIsTaken;
834 TII.storeRegToStackSlot(MBB, MI, Reg, IsKill,
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| /src/external/apache2/llvm/dist/llvm/lib/Target/M68k/ |
| M68kInstrBuilder.h | 50 bool IsKill, int Offset) {
51 return MIB.addImm(Offset).addReg(Reg, getKillRegState(IsKill));
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| M68kInstrInfo.h | 282 bool IsKill, int FrameIndex,
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| M68kInstrInfo.cpp | 757 Register SrcReg, bool IsKill,
768 .addReg(SrcReg, getKillRegState(IsKill));
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| /src/external/apache2/llvm/dist/llvm/lib/CodeGen/ |
| FixupStatepointCallerSaved.cpp | 112 // IsKill - set to true if COPY is Kill (there are no uses of Y)
116 bool &IsKill, const TargetInstrInfo &TII,
121 IsKill = false;
158 IsKill = DestSrc->Source->isKill();
418 bool IsKill = true;
420 Reg = performCopyPropagation(Reg, InsertBefore, IsKill, TII, TRI);
423 TII.storeRegToStackSlot(*MI.getParent(), InsertBefore, Reg, IsKill, FI,
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| ScheduleDAGInstrs.cpp | 403 bool IsKill = MO.getSubReg() == 0 || MO.isUndef();
407 KillLaneMask = IsKill ? LaneBitmask::getAll() : DefLaneMask;
1108 bool IsKill = LiveRegs.available(MRI, Reg);
1109 MO.setIsKill(IsKill);
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| /src/external/apache2/llvm/dist/llvm/lib/Target/BPF/ |
| BPFInstrInfo.cpp | 126 Register SrcReg, bool IsKill, int FI,
135 .addReg(SrcReg, getKillRegState(IsKill))
140 .addReg(SrcReg, getKillRegState(IsKill))
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| /src/external/apache2/llvm/dist/llvm/lib/Target/Lanai/ |
| LanaiInstrInfo.h | 57 Register SourceRegister, bool IsKill, int FrameIndex,
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| LanaiInstrInfo.cpp | 51 Register SourceRegister, bool IsKill, int FrameIndex,
63 .addReg(SourceRegister, getKillRegState(IsKill))
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| /src/external/apache2/llvm/dist/llvm/lib/Target/RISCV/ |
| RISCVInstrInfo.h | 45 bool IsKill, int FrameIndex,
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| RISCVInstrInfo.cpp | 244 Register SrcReg, bool IsKill, int FI,
314 .addReg(SrcReg, getKillRegState(IsKill))
329 .addReg(SrcReg, getKillRegState(IsKill))
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| /src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/ |
| AArch64AdvSIMDScalarPass.cpp | 275 unsigned Dst, unsigned Src, bool IsKill) {
278 .addReg(Src, getKillRegState(IsKill));
310 KillSrc0 = MOSrc0->isKill();
329 KillSrc1 = MOSrc1->isKill();
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| AArch64InstrInfo.cpp | 3579 Register SrcReg, bool IsKill,
3591 .addReg(SrcReg0, getKillRegState(IsKill), SubIdx0)
3592 .addReg(SrcReg1, getKillRegState(IsKill), SubIdx1)
3600 bool isKill, int FI, const TargetRegisterClass *RC,
3647 get(AArch64::STPWi), SrcReg, isKill,
3661 get(AArch64::STPXi), SrcReg, isKill,
3719 .addReg(SrcReg, getKillRegState(isKill))
4155 storeRegToStackSlot(MBB, InsertPt, SrcReg, SrcMO.isKill(), FrameIndex,
4204 storeRegToStackSlot(MBB, InsertPt, WidenedSrcReg, SrcMO.isKill(),
5016 bool Src0IsKill = MUL->getOperand(1).isKill();
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/ |
| SIRegisterInfo.cpp | 82 bool IsKill;
114 IsKill(MI->getOperand(0).isKill()), DL(MI->getDebugLoc()), Index(Index),
202 /*IsKill*/ false);
225 /*IsKill*/ false);
237 /*IsKill*/ false);
262 /*IsKill*/ false);
921 unsigned ValueReg, bool IsKill) {
941 .addReg(Src, getKillRegState(IsKill));
1023 unsigned LoadStoreOp, int Index, Register ValueReg, bool IsKill,
[all...] |
| SIShrinkInstructions.cpp | 245 bool IsKill = NewAddrDwords == Info->VAddrDwords;
257 if (!Op.isKill())
258 IsKill = false;
292 MI.getOperand(VAddr0Idx).setIsKill(IsKill);
367 const bool IsKill = SrcReg->isKill();
374 /*isImp*/ false, IsKill,
583 if (Op.isKill() && TRI.regsOverlap(X, Op.getReg()))
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| SIRegisterInfo.h | 112 bool IsLoad, bool IsKill = true) const;
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| SIInstrInfo.cpp | 1406 Register SrcReg, bool isKill,
1440 .addReg(SrcReg, getKillRegState(isKill)) // data
1455 .addReg(SrcReg, getKillRegState(isKill)) // data
2045 bool IsKill = RegOp.isKill();
2063 NonRegOp.ChangeToRegister(Reg, false, false, IsKill, IsDead, IsUndef, IsDebug);
2415 CondReg.setIsKill(OrigCond.isKill());
2470 CondReg.setIsKill(Cond[1].isKill());
2817 Src0->setIsKill(Src1->isKill());
3037 if (Op.isReg() && Op.isKill())
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/ |
| HexagonFrameLowering.h | 175 bool IsDef, bool IsKill) const;
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| HexagonFrameLowering.cpp | 1419 bool IsKill = !HRI.isEHReturnCalleeSaveReg(Reg);
1422 HII.storeRegToStackSlot(MBB, MI, Reg, IsKill, FI, RC, &HRI);
1423 if (IsKill)
1782 bool IsKill = MI->getOperand(2).isKill();
1791 .addReg(SrcR, getKillRegState(IsKill));
1845 bool IsKill = MI->getOperand(2).isKill();
1860 .addReg(SrcR, getKillRegState(IsKill))
1934 bool IsKill = MI->getOperand(2).isKill()
[all...] |
| HexagonBlockRanges.cpp | 326 bool IsKill = Op.isKill();
329 if (IsKill)
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| /src/external/apache2/llvm/dist/llvm/lib/Target/ARM/ |
| ARMLoadStoreOptimizer.cpp | 870 bool IsKill = MO.isKill();
871 if (IsKill)
873 Regs.push_back(std::make_pair(Reg, IsKill));
964 if (!MO.isReg() || !MO.isKill())
1293 bool BaseKill = BaseOP.isKill();
1473 bool BaseKill = getLoadStoreBaseOp(*MI).isKill();
1534 : getKillRegState(MO.isKill())))
1586 .addReg(MO.getReg(), getKillRegState(MO.isKill()))
1597 .addReg(MO.getReg(), getKillRegState(MO.isKill()))
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/X86/ |
| X86InstrInfo.cpp | 1191 bool &isKill, MachineOperand &ImplicitOp,
1207 isKill = Src.isKill();
1223 isKill = Src.isKill();
1235 isKill = true;
1279 bool IsKill = MI.getOperand(1).isKill();
1286 .addReg(Src, getKillRegState(IsKill));
1320 bool IsKill2 = MI.getOperand(2).isKill();
[all...] |
