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    Searched refs:IsPre (Results 1 - 4 of 4) sorted by relevancy

  /src/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/GlobalISel/
CombinerHelper.h 50 bool IsPre;
222 /// $val, $addr = G_INDEXED_LOAD $base, $offset, 1 (IsPre)
  /src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/
AArch64ISelDAGToDAG.cpp 1275 bool IsPre = AM == ISD::PRE_INC || AM == ISD::PRE_DEC;
1285 Opcode = IsPre ? AArch64::LDRXpre : AArch64::LDRXpost;
1288 Opcode = IsPre ? AArch64::LDRWpre : AArch64::LDRWpost;
1290 Opcode = IsPre ? AArch64::LDRSWpre : AArch64::LDRSWpost;
1292 Opcode = IsPre ? AArch64::LDRWpre : AArch64::LDRWpost;
1301 Opcode = IsPre ? AArch64::LDRSHXpre : AArch64::LDRSHXpost;
1303 Opcode = IsPre ? AArch64::LDRSHWpre : AArch64::LDRSHWpost;
1305 Opcode = IsPre ? AArch64::LDRHHpre : AArch64::LDRHHpost;
1314 Opcode = IsPre ? AArch64::LDRSBXpre : AArch64::LDRSBXpost;
1316 Opcode = IsPre ? AArch64::LDRSBWpre : AArch64::LDRSBWpost
    [all...]
  /src/external/apache2/llvm/dist/llvm/lib/CodeGen/GlobalISel/
CombinerHelper.cpp 775 !TLI.isIndexingLegal(MI, Base, Offset, /*IsPre*/ false, MRI)) {
841 !TLI.isIndexingLegal(MI, Base, Offset, /*IsPre*/ true, MRI)) {
900 MatchInfo.IsPre = findPreIndexCandidate(MI, MatchInfo.Addr, MatchInfo.Base,
902 if (!MatchInfo.IsPre &&
945 MIB.addImm(MatchInfo.IsPre);
  /src/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/
TargetLowering.h 3197 bool IsPre, MachineRegisterInfo &MRI) const {

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