HomeSort by: relevance | last modified time | path
    Searched refs:IsStore (Results 1 - 19 of 19) sorted by relevancy

  /src/external/apache2/llvm/dist/llvm/lib/Target/Mips/MCTargetDesc/
MipsMCNaCl.h 21 bool *IsStore = nullptr);
MipsNaClELFStreamer.cpp 158 bool IsStore = false;
160 &IsStore);
166 bool MaskAfter = IsSPFirstOperand && !IsStore;
211 bool *IsStore) {
212 if (IsStore)
213 *IsStore = false;
243 if (IsStore)
244 *IsStore = true;
251 if (IsStore)
252 *IsStore = true
    [all...]
  /src/external/apache2/llvm/dist/llvm/lib/Target/M68k/
M68kCollapseMOVEMPass.cpp 145 bool isStore() const { return Access == AccessTy::Store; }
204 bool IsStore = false) {
209 if (State.isStore() == IsStore && State.getBase() == Reg &&
218 return ProcessMI(MBB, MI, State, Mask, Offset, Reg, IsStore);
227 IsStore ? State.setStore() : State.setLoad();
  /src/external/apache2/llvm/dist/llvm/lib/Target/ARC/
ARCOptAddrMode.cpp 395 bool IsStore = Ldst->mayStore();
402 if (IsStore && MI->mayLoad())
423 bool IsStore = Ldst->mayStore();
433 if (IsStore && MI->mayLoad())
444 bool IsStore = Ldst.mayStore();
454 if (IsStore) {
461 if (IsStore)
  /src/external/apache2/llvm/dist/llvm/lib/Target/PowerPC/
PPCVSXSwapRemoval.cpp 75 unsigned int IsStore : 1;
367 SwapVector[VecIdx].IsStore = 1;
373 SwapVector[VecIdx].IsStore = 1;
681 SwapVector[UseIdx].IsStore) {
698 !SwapVector[UseIdx].IsStore) {
703 if (SwapVector[UseOfUseIdx].IsStore) {
720 } else if (SwapVector[EntryIdx].IsStore && SwapVector[EntryIdx].IsSwap) {
728 SwapVector[DefIdx].IsStore) {
794 } else if (SwapVector[EntryIdx].IsStore && SwapVector[EntryIdx].IsSwap) {
1006 if (SwapVector[EntryIdx].IsStore)
    [all...]
  /src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/
SIRegisterInfo.cpp 931 bool IsStore = MI->mayStore();
935 unsigned Dst = IsStore ? Reg : ValueReg;
936 unsigned Src = IsStore ? ValueReg : Reg;
937 unsigned Opc = (IsStore ^ TRI->isVGPR(MRI, Reg)) ? AMDGPU::V_ACCVGPR_WRITE_B32_e64
956 bool IsStore = MI->mayStore();
959 int LoadStoreOp = IsStore ?
989 bool IsStore = TII->get(LoadStoreOp).mayStore();
996 LoadStoreOp = IsStore ? AMDGPU::SCRATCH_STORE_DWORD_SADDR
1000 LoadStoreOp = IsStore ? AMDGPU::SCRATCH_STORE_DWORDX2_SADDR
1004 LoadStoreOp = IsStore ? AMDGPU::SCRATCH_STORE_DWORDX3_SADD
    [all...]
AMDGPULegalizerInfo.cpp 1082 const bool IsStore = Op == G_STORE;
1137 if (!IsStore) {
1255 if (IsStore)
  /src/external/apache2/llvm/dist/llvm/utils/TableGen/
X86FoldTablesEmitter.cpp 104 bool IsStore = false;
121 if (IsStore)
479 Result.IsStore = true;
  /src/external/apache2/llvm/dist/clang/include/clang/Basic/
TargetBuiltins.h 246 bool isStore() const { return Flags & IsStore; }
  /src/external/apache2/llvm/dist/llvm/lib/Target/ARM/
Thumb2SizeReduction.cpp 466 bool IsStore = Entry.WideOpc == ARM::t2STR_POST;
467 Register Rt = MI->getOperand(IsStore ? 1 : 0).getReg();
468 Register Rn = MI->getOperand(IsStore ? 0 : 1).getReg();
485 .addReg(Rt, IsStore ? 0 : RegState::Define);
ARMLoadStoreOptimizer.cpp 500 bool IsStore =
503 if (IsLoad || IsStore) {
516 if (Offset >= 0 && !(IsStore && InstrSrcReg == Base))
  /src/external/apache2/llvm/dist/clang/lib/CodeGen/
CGAtomic.cpp 1288 bool IsStore = E->getOp() == AtomicExpr::AO__c11_atomic_store ||
1309 if (IsStore)
1321 if (IsLoad || IsStore)
1347 if (!IsStore)
1351 if (!IsLoad && !IsStore)
1368 if (!IsStore) {
1386 if (!IsLoad && !IsStore) {
  /src/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/
HexagonExpandCondsets.cpp 823 bool IsLoad = TheI.mayLoad(), IsStore = TheI.mayStore();
824 if (!IsLoad && !IsStore)
846 bool Conflict = (L && IsStore) || S;
HexagonConstExtenders.cpp 1146 bool IsStore = MI.mayStore();
1155 if (IsLoad || IsStore) {
  /src/external/apache2/llvm/dist/llvm/lib/Target/X86/
X86MCInstLower.cpp 376 bool IsStore = Inst.getOperand(0).isReg() && Inst.getOperand(1).isReg();
377 unsigned AddrBase = IsStore;
378 unsigned RegOp = IsStore ? 0 : 5;
X86TargetTransformInfo.cpp 3441 bool IsStore = (Instruction::Store == Opcode);
3452 (IsStore && !isLegalMaskedStore(SrcVTy, Alignment)) ||
3464 getScalarizationOverhead(SrcVTy, DemandedElts, IsLoad, IsStore);
  /src/external/apache2/llvm/dist/llvm/lib/CodeGen/GlobalISel/
CombinerHelper.cpp 915 bool IsStore = Opcode == TargetOpcode::G_STORE;
935 if (IsStore) {
  /src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/
AArch64ISelLowering.cpp 14846 bool IsStore = false;
14861 NumVecs = 2; IsStore = true; break;
14863 NumVecs = 3; IsStore = true; break;
14865 NumVecs = 4; IsStore = true; break;
14873 NumVecs = 2; IsStore = true; break;
14875 NumVecs = 3; IsStore = true; break;
14877 NumVecs = 4; IsStore = true; break;
14891 NumVecs = 2; IsStore = true; IsLaneOp = true; break;
14893 NumVecs = 3; IsStore = true; IsLaneOp = true; break;
14895 NumVecs = 4; IsStore = true; IsLaneOp = true; break
    [all...]
  /src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/GISel/
AArch64InstructionSelector.cpp 737 const bool isStore = GenericOpc == TargetOpcode::G_STORE;
742 return isStore ? AArch64::STRBBui : AArch64::LDRBBui;
744 return isStore ? AArch64::STRHHui : AArch64::LDRHHui;
746 return isStore ? AArch64::STRWui : AArch64::LDRWui;
748 return isStore ? AArch64::STRXui : AArch64::LDRXui;
754 return isStore ? AArch64::STRBui : AArch64::LDRBui;
756 return isStore ? AArch64::STRHui : AArch64::LDRHui;
758 return isStore ? AArch64::STRSui : AArch64::LDRSui;
760 return isStore ? AArch64::STRDui : AArch64::LDRDui;
2636 bool IsStore = I.getOpcode() == TargetOpcode::G_STORE
    [all...]

Completed in 111 milliseconds