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    Searched refs:IsUndef (Results 1 - 18 of 18) sorted by relevancy

  /src/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/
MachineOperand.h 115 /// IsUndef - True if this register operand reads an "undef" value, i.e. the
132 unsigned IsUndef : 1;
395 bool isUndef() const {
397 return IsUndef;
460 return !isUndef() && !isInternalRead() && (isUse() || getSubReg());
513 IsUndef = Val;
718 /// for liveness related flags (isKill, isUndef and isDead). Note that this
762 bool isUndef = false, bool isDebug = false);
793 bool isUndef = false,
805 Op.IsUndef = isUndef
    [all...]
MachineInstr.h 1590 void setRegisterDefReadUndef(Register Reg, bool IsUndef = true);
  /src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/
SIShrinkInstructions.cpp 244 bool IsUndef = true;
255 if (!Op.isUndef())
256 IsUndef = false;
291 MI.getOperand(VAddr0Idx).setIsUndef(IsUndef);
366 const bool IsUndef = SrcReg->isUndef();
375 /*isDead*/ false, IsUndef);
GCNHazardRecognizer.cpp 898 bool IsUndef = Src0->isUndef();
901 .addReg(Reg, RegState::Define | (IsUndef ? RegState::Dead : 0))
902 .addReg(Reg, IsUndef ? RegState::Undef : RegState::Kill);
SIInstrInfo.cpp 1815 bool IsUndef = MI.getOperand(1).isUndef();
1824 .addReg(VecReg, RegState::Implicit | (IsUndef ? RegState::Undef : 0));
1843 bool IsUndef = MI.getOperand(1).isUndef();
1859 RegState::Implicit | (IsUndef ? RegState::Undef : 0));
1883 bool IsUndef = MI.getOperand(1).isUndef();
1895 .addReg(VecReg, RegState::Implicit | (IsUndef ? RegState::Undef : 0))
1997 MovDPP.addReg(Src, SrcOp.isUndef() ? RegState::Undef : 0, Sub)
    [all...]
  /src/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/GlobalISel/
CombinerHelper.h 180 /// In the first case \p IsUndef will be true.
185 bool matchCombineConcatVectors(MachineInstr &MI, bool &IsUndef,
188 /// implicit_def if IsUndef is true.
189 void applyCombineConcatVectors(MachineInstr &MI, bool IsUndef,
  /src/external/apache2/llvm/dist/clang/include/clang/Basic/
TargetBuiltins.h 264 bool isUndef() const { return Flags & IsUndef; }
  /src/external/apache2/llvm/dist/llvm/lib/CodeGen/GlobalISel/
CombinerHelper.cpp 166 bool IsUndef = false;
168 if (matchCombineConcatVectors(MI, IsUndef, Ops)) {
169 applyCombineConcatVectors(MI, IsUndef, Ops);
175 bool CombinerHelper::matchCombineConcatVectors(MachineInstr &MI, bool &IsUndef,
179 IsUndef = true;
191 IsUndef = false;
221 MachineInstr &MI, bool IsUndef, const ArrayRef<Register> Ops) {
228 // Note: IsUndef is sort of redundant. We could have determine it by
234 if (IsUndef)
LegalizerHelper.cpp 5142 const bool IsUndef = MI.getOpcode() == TargetOpcode::G_CTLZ_ZERO_UNDEF;
5150 auto LoCTLZ = IsUndef ?
5178 const bool IsUndef = MI.getOpcode() == TargetOpcode::G_CTTZ_ZERO_UNDEF;
5186 auto HiCTTZ = IsUndef ?
  /src/external/apache2/llvm/dist/llvm/lib/CodeGen/
MachineInstr.cpp 1025 Use |= !MO.isUndef();
1026 else if (MO.getSubReg() && !MO.isUndef())
1888 if (!MO.isReg() || !MO.isUse() || MO.isUndef())
2018 void MachineInstr::setRegisterDefReadUndef(Register Reg, bool IsUndef) {
2022 MO.setIsUndef(IsUndef);
MachineOperand.cpp 242 bool isKill, bool isDead, bool isUndef,
263 IsUndef = isUndef;
755 if (isUndef())
RegisterCoalescer.cpp 914 if (UseMO.isUndef())
1253 if (Op.getSubReg() == 0 || Op.isUndef())
1299 if (DstOperand.getSubReg() && !DstOperand.isUndef())
1655 if (MO.isDef() /*|| MO.isUndef()*/)
1697 bool IsUndef = true;
1702 IsUndef = false;
1706 if (IsUndef) {
1726 if (SubReg == 0 || MO.isUndef())
1848 if (SubRegIdx == 0 || MO.isUndef())
3086 if (MO.getSubReg() != 0 && MO.isUndef() && !EraseImpDef
    [all...]
  /src/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/
HexagonISelLoweringHVX.cpp 512 bool IsSplat = true, IsUndef = true;
515 if (isUndef(Words[i]))
517 IsUndef = false;
523 if (IsUndef)
561 if (isUndef(V)) {
695 SDValue W0 = isUndef(PredV)
765 SDValue Ext = !V.isUndef() ? DAG.getZExtOrTrunc(V, dl, MVT::i8)
778 if (!Values[I+B].isUndef())
791 assert(Values[I+B].isUndef() || Values[I+B] == F);
1717 if (isUndef(Thru)
    [all...]
  /src/external/apache2/llvm/dist/llvm/lib/Analysis/
InstructionSimplify.cpp 4807 bool IsUndef = Q.isUndefValue(V);
4812 if (FMF.noNaNs() && (IsNan || IsUndef))
4814 if (FMF.noInfs() && (IsInf || IsUndef))
4817 if (IsUndef || IsNan)
  /src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/
AArch64InstrInfo.cpp 3736 bool IsUndef = true;
3742 IsUndef = false;
3745 .addReg(DestReg0, RegState::Define | getUndefRegState(IsUndef), SubIdx0)
3746 .addReg(DestReg1, RegState::Define | getUndefRegState(IsUndef), SubIdx1)
4172 if (IsSpill && DstMO.isUndef() && Register::isPhysicalRegister(SrcReg)) {
4219 if (IsFill && SrcMO.getSubReg() == 0 && DstMO.isUndef()) {
  /src/external/apache2/llvm/dist/llvm/bindings/go/llvm/
ir.go 810 func (v Value) IsUndef() bool { return C.LLVMIsUndef(v.C) != 0 }
  /src/external/apache2/llvm/dist/clang/lib/Serialization/
ASTReader.cpp 459 llvm::StringMap<std::pair<StringRef, bool /*IsUndef*/>>;
594 bool IsUndef = PPOpts.Macros[I].second;
601 if (IsUndef) {
651 llvm::StringMap<std::pair<StringRef, bool /*IsUndef*/>>::iterator Known =
5880 bool IsUndef = Record[Idx++];
5881 PPOpts.Macros.push_back(std::make_pair(Macro, IsUndef));
  /src/external/apache2/llvm/dist/llvm/lib/Target/X86/
X86ISelLowering.cpp 5804 bool IsUndef = Values[i] < 0 && IsMask;
5805 SDValue OpNode = IsUndef ? DAG.getUNDEF(EltVT) :
5809 Ops.push_back(IsUndef ? DAG.getUNDEF(EltVT) :
5936 if (Vec.isUndef())
6160 if (SubVec.isUndef())
6163 if (IdxVal == 0 && Vec.isUndef()) // the operation is legal
6211 if (Vec.isUndef()) {
6607 if (Op.isUndef()) {
6635 if (Src.isUndef()) {
6652 if (Src.isUndef()) {
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