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    Searched refs:IsVector (Results 1 - 13 of 13) sorted by relevancy

  /src/external/apache2/llvm/dist/llvm/include/llvm/Support/
LowLevelTypeImpl.h 45 return LLT{/*isPointer=*/false, /*isVector=*/false, /*NumElements=*/0,
52 return LLT{/*isPointer=*/true, /*isVector=*/false, /*NumElements=*/0,
61 return LLT{/*isPointer=*/false, /*isVector=*/true, NumElements,
68 assert(!ScalarTy.isVector() && "invalid vector element type");
69 return LLT{ScalarTy.isPointer(), /*isVector=*/true, NumElements,
82 explicit LLT(bool isPointer, bool isVector, uint16_t NumElements,
84 init(isPointer, isVector, NumElements, SizeInBits, AddressSpace);
86 explicit LLT() : IsPointer(false), IsVector(false), RawData(0) {}
92 bool isScalar() const { return isValid() && !IsPointer && !IsVector; }
94 bool isPointer() const { return isValid() && IsPointer && !IsVector; }
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  /src/external/apache2/llvm/dist/llvm/lib/Support/
LowLevelType.cpp 19 if (VT.isVector()) {
27 init(/*IsPointer=*/false, /*IsVector=*/false, /*NumElements=*/0,
31 IsVector = false;
37 if (isVector())
  /src/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/GlobalISel/
Utils.h 376 bool isConstTrueVal(const TargetLowering &TLI, int64_t Val, bool IsVector,
381 int64_t getICmpTrueVal(const TargetLowering &TLI, bool IsVector, bool IsFP);
  /src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/
R600ExpandSpecialInstrs.cpp 164 bool IsVector = TII->isVector(MI);
166 if (!IsReduction && !IsVector && !IsCube) {
  /src/external/apache2/llvm/dist/llvm/lib/CodeGen/GlobalISel/
Utils.cpp 766 if (OrigTy.isVector()) {
769 if (TargetTy.isVector()) {
788 if (TargetTy.isVector()) {
811 if (OrigTy.isVector()) {
813 if (TargetTy.isVector()) {
837 if (TargetTy.isVector()) {
969 bool llvm::isConstTrueVal(const TargetLowering &TLI, int64_t Val, bool IsVector,
971 switch (TLI.getBooleanContents(IsVector, IsFP)) {
982 int64_t llvm::getICmpTrueVal(const TargetLowering &TLI, bool IsVector,
984 switch (TLI.getBooleanContents(IsVector, IsFP))
    [all...]
CombinerHelper.cpp 261 unsigned DstNumElts = DstType.isVector() ? DstType.getNumElements() : 1;
262 unsigned SrcNumElts = SrcType.isVector() ? SrcType.getNumElements() : 1;
661 if (MRI.getType(SrcReg).isVector())
695 if (MRI.getType(MI.getOperand(0).getReg()).isVector())
1147 if (NewTy.isVector())
1181 if (Ty.isVector())
1192 if (!Ty.isVector() && ValVRegAndVal) {
1214 if (Ty.isVector())
1305 if (!LargestTy.isVector() && !Ty.isVector() &
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  /src/external/apache2/llvm/dist/llvm/lib/Target/ARM/MCTargetDesc/
ARMELFStreamer.cpp 86 bool isVector) override;
158 bool isVector) {
160 if (isVector)
390 bool isVector) override;
459 void emitRegSave(const SmallVectorImpl<unsigned> &RegList, bool isVector);
762 bool isVector) {
763 getStreamer().emitRegSave(RegList, isVector);
1467 bool IsVector) {
1474 assert(Reg < (IsVector ? 32U : 16U) && "Register out of range");
1486 SPOffset -= Count * (IsVector ? 8 : 4)
    [all...]
  /src/external/gpl3/gcc.old/dist/libstdc++-v3/include/pstl/
algorithm_fwd.h 367 class IsVector>
370 IsVector,
374 class IsVector>
377 _BinaryPredicate, IsVector,
826 /* IsVector = */ std::true_type, bool) noexcept;
831 /* IsVector = */ std::false_type, bool) noexcept;
  /src/external/apache2/llvm/dist/llvm/include/llvm/AsmParser/
LLParser.h 413 bool parseArrayVectorType(Type *&Result, bool IsVector);
  /src/external/apache2/llvm/dist/clang/lib/CodeGen/
CGExpr.cpp 1792 bool IsVector = true) {
1795 if (ArrayTy && IsVector) {
1803 if (VectorTy && !IsVector) {
TargetInfo.cpp 7424 bool IsVector = false;
7434 IsVector = ArgTy->isVectorTy();
7439 if (IsVector && UnpaddedSize > PaddedSize)
7449 if (IsVector) {
  /src/external/apache2/llvm/dist/llvm/lib/AsmParser/
LLParser.cpp 3033 bool LLParser::parseArrayVectorType(Type *&Result, bool IsVector) {
3036 if (IsVector && Lex.getKind() == lltok::kw_vscale) {
3060 if (parseToken(IsVector ? lltok::greater : lltok::rsquare,
3064 if (IsVector) {
  /src/external/apache2/llvm/dist/llvm/lib/Target/ARM/AsmParser/
ARMAsmParser.cpp 480 bool parseDirectiveRegSave(SMLoc L, bool IsVector);
11671 bool ARMAsmParser::parseDirectiveRegSave(SMLoc L, bool IsVector) {
11686 if (!IsVector && !Op.isRegList())
11688 if (IsVector && !Op.isDPRRegList())
11691 getTargetStreamer().emitRegSave(Op.getRegList(), IsVector);

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