| /src/sys/arch/riscv/riscv/ |
| db_machdep.c | 137 || (OPCODE_P(insn, JALR) && ri.type_i.i_rd == 1);
145 return OPCODE_P(insn, JAL) || OPCODE_P(insn, JALR);
152 return OPCODE_P(insn, JALR) && ri.type_i.i_rs1 == 1;
179 if (OPCODE_P(insn, JALR)) {
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| /src/external/apache2/llvm/dist/llvm/lib/Target/Mips/MCTargetDesc/ |
| MipsNaClELFStreamer.cpp | 59 if (MI.getOpcode() == Mips::JALR) {
60 // MIPS32r6/MIPS64r6 doesn't have a JR instruction and uses JALR instead.
61 // JALR is an indirect branch if the link register is $0.
89 case Mips::JALR:
90 // JALR is only a call if the link register is not $0. Otherwise it's an
|
| MipsInstPrinter.cpp | 248 case Mips::JALR:
249 // jalr $ra, $r1 => jalr $r1
250 return isReg<Mips::RA>(MI, 0) && printAlias("jalr", MI, 1, OS);
252 // jalr $ra, $r1 => jalr $r1
253 return isReg<Mips::RA_64>(MI, 0) && printAlias("jalr", MI, 1, OS);
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/RISCV/MCTargetDesc/ |
| RISCVMCCodeEmitter.cpp | 101 // Expand PseudoCALL(Reg), PseudoTAIL and PseudoJump to AUIPC and JALR with
103 // meaning AUIPC and JALR won't go through RISCV MC to MC compressed
106 // deal with it. When linker relaxation is enabled, AUIPC and JALR have a
143 // Emit JALR X0, Ra, 0
144 TmpInst = MCInstBuilder(RISCV::JALR).addReg(RISCV::X0).addReg(Ra).addImm(0);
146 // Emit JALR Ra, Ra, 0
147 TmpInst = MCInstBuilder(RISCV::JALR).addReg(Ra).addReg(Ra).addImm(0);
|
| /src/sys/arch/mips/mips/ |
| bds_emul.S | 273 PTR_WORD bcemul_sigill # 011 JALR
377 jr ra; nop # 011 JALR
|
| /src/sys/external/bsd/sljit/dist/sljit_src/ |
| sljitNativeMIPS_common.c | 139 #define JALR (HI(0) | LO(9))
1674 PTR_FAIL_IF(push_inst(compiler, JALR | S(TMP_REG2) | DA(RETURN_ADDR_REG), UNMOVABLE_INS));
1857 FAIL_IF(push_inst(compiler, JALR | S(PIC_ADDR_REG) | DA(RETURN_ADDR_REG), UNMOVABLE_INS));
1865 FAIL_IF(push_inst(compiler, JALR | S(src_r) | DA(RETURN_ADDR_REG), UNMOVABLE_INS));
|
| /src/external/gpl3/gdb.old/dist/gdb/ |
| riscv-tdep.c | 1572 JALR,
1904 decode_i_type_insn (JALR, ival);
1991 decode_cr_type_insn (JALR, ival);
2060 decode_cr_type_insn (JALR, ival);
2273 else if (insn.opcode () == riscv_insn::JALR
4443 else if (insn.opcode () == riscv_insn::JALR)
4614 jumps, taken backward branches, JALR, FENCE, FENCE.I, and SYSTEM
|
| /src/external/gpl3/gdb/dist/gdb/ |
| riscv-tdep.c | 1589 JALR,
1921 decode_i_type_insn (JALR, ival);
2008 decode_cr_type_insn (JALR, ival);
2077 decode_cr_type_insn (JALR, ival);
2290 else if (insn.opcode () == riscv_insn::JALR
4484 else if (insn.opcode () == riscv_insn::JALR)
4655 jumps, taken backward branches, JALR, FENCE, FENCE.I, and SYSTEM
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/Mips/ |
| MipsAsmPrinter.cpp | 114 // JALR, or JALR64 as appropriate for the target.
126 // MIPS32r6 should use (JALR ZERO, $rs)
130 TmpInst0.setOpcode(Mips::JALR);
1163 // JALR T9
1200 // JALR T9
|
| MipsDelaySlotFiller.cpp | 590 case Mips::JALR:
|
| MipsInstrInfo.cpp | 793 case Mips::JALR:
841 {MO_JALR, "mips-jalr"}
|
| MipsSEISelDAGToDAG.cpp | 194 case Mips::JALR:
|
| MipsFastISel.cpp | 1559 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Mips::JALR),
|
| MipsISelLowering.cpp | 3084 case Mips::JALR:
|
| /src/external/gpl3/binutils/dist/bfd/ |
| elfnn-riscv.c | 407 entry[7] = RISCV_ITYPE (JALR, 0, X_T3, 0);
462 header[8] = RISCV_ITYPE (JALR, 0, X_T3, 0);
491 jalr t1, t3
497 entry[2] = RISCV_ITYPE (JALR, X_T1, X_T3, 0);
515 jalr t1, t3 */
532 entry[3] = RISCV_ITYPE (JALR, X_T1, X_T3, 0);
4900 /* Relax AUIPC + JALR into JAL. */
4916 bfd_vma auipc, jalr; local
4939 jalr = bfd_getl32 (contents + rel->r_offset + 4);
4940 rd = (jalr >> OP_SH_RD) & OP_MASK_RD
[all...] |
| /src/external/gpl3/binutils.old/dist/bfd/ |
| elfnn-riscv.c | 407 entry[7] = RISCV_ITYPE (JALR, 0, X_T3, 0);
462 header[8] = RISCV_ITYPE (JALR, 0, X_T3, 0);
491 jalr t1, t3
497 entry[2] = RISCV_ITYPE (JALR, X_T1, X_T3, 0);
515 jalr t1, t3 */
532 entry[3] = RISCV_ITYPE (JALR, X_T1, X_T3, 0);
4866 /* Relax AUIPC + JALR into JAL. */
4882 bfd_vma auipc, jalr; local
4905 jalr = bfd_getl32 (contents + rel->r_offset + 4);
4906 rd = (jalr >> OP_SH_RD) & OP_MASK_RD
[all...] |
| /src/external/gpl3/gdb/dist/bfd/ |
| elfnn-riscv.c | 407 entry[7] = RISCV_ITYPE (JALR, 0, X_T3, 0);
462 header[8] = RISCV_ITYPE (JALR, 0, X_T3, 0);
491 jalr t1, t3
497 entry[2] = RISCV_ITYPE (JALR, X_T1, X_T3, 0);
515 jalr t1, t3 */
532 entry[3] = RISCV_ITYPE (JALR, X_T1, X_T3, 0);
4872 /* Relax AUIPC + JALR into JAL. */
4888 bfd_vma auipc, jalr; local
4911 jalr = bfd_getl32 (contents + rel->r_offset + 4);
4912 rd = (jalr >> OP_SH_RD) & OP_MASK_RD
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/RISCV/ |
| RISCVInstrInfo.cpp | 1116 MBB.insert(MBB.end(), BuildMI(MF, DebugLoc(), get(RISCV::JALR))
|
| /src/external/gpl3/gdb.old/dist/bfd/ |
| elfnn-riscv.c | 350 entry[7] = RISCV_ITYPE (JALR, 0, X_T3, 0);
371 jalr t1, t3
376 entry[2] = RISCV_ITYPE (JALR, X_T1, X_T3, 0);
4631 /* Relax AUIPC + JALR into JAL. */
4647 bfd_vma auipc, jalr; local
4670 jalr = bfd_getl32 (contents + rel->r_offset + 4);
4671 rd = (jalr >> OP_SH_RD) & OP_MASK_RD;
4692 /* Near zero, relax to JALR rd, x0, addr. */
4702 /* Delete unnecessary JALR and reuse the R_RISCV_RELAX reloc. */
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/Mips/AsmParser/ |
| MipsAsmParser.cpp | 2131 JalrInst.setOpcode(Mips::JALR);
2136 // As an optimization hint for the linker, before the JALR we add:
2356 // We need a NOP between the JALR and the LW:
2640 // Create a JALR instruction which is going to replace the pseudo-JAL.
2647 // jal $rs => jalr $rs
2655 JalrInst.setOpcode(Mips::JALR);
2660 // jal $rd, $rs => jalr $rd, $rs
2664 JalrInst.setOpcode(inMicroMipsMode() ? Mips::JALR_MM : Mips::JALR);
5784 // jalr.hb must be different.
|
