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    Searched refs:JH7110_STGCLK_PCIE0_AXI_MST0 (Results 1 - 3 of 3) sorted by relevancy

/src/sys/external/gpl2/dts/dist/include/dt-bindings/clock/
starfive,jh7110-crg.h	237 #define JH7110_STGCLK_PCIE0_AXI_MST0 8
/src/sys/arch/riscv/starfive/
jh7110_clkc.c	273 #define JH7110_STGCLK_PCIE0_AXI_MST0 8 716 JH71X0CLKC_GATE(JH7110_STGCLK_PCIE0_AXI_MST0, "pcie0_axi_mst0", "stg_axiahb"),
/src/sys/external/gpl2/dts/dist/arch/riscv/boot/dts/starfive/
jh7110.dtsi	1247 <&stgcrg JH7110_STGCLK_PCIE0_AXI_MST0>,

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