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    Searched refs:JH7110_STGCLK_USB0_AXI (Results 1 - 3 of 3) sorted by relevancy

/src/sys/external/gpl2/dts/dist/include/dt-bindings/clock/
starfive,jh7110-crg.h	232 #define JH7110_STGCLK_USB0_AXI 3
/src/sys/arch/riscv/starfive/
jh7110_clkc.c	268 #define JH7110_STGCLK_USB0_AXI 3 710 JH71X0CLKC_GATE(JH7110_STGCLK_USB0_AXI, "usb0_axi", "stg_axiahb"),
/src/sys/external/gpl2/dts/dist/arch/riscv/boot/dts/starfive/
jh7110.dtsi	579 <&stgcrg JH7110_STGCLK_USB0_AXI>,

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