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    Searched refs:JH7110_SYSCLK_UART5_CORE (Results 1 - 3 of 3) sorted by relevancy

/src/sys/external/gpl2/dts/dist/include/dt-bindings/clock/
starfive,jh7110-crg.h	173 #define JH7110_SYSCLK_UART5_CORE 156
/src/sys/arch/riscv/starfive/
jh7110_clkc.c	204 #define JH7110_SYSCLK_UART5_CORE 156 616 JH71X0CLKC_GATEDIV(JH7110_SYSCLK_UART5_CORE, "uart5_core",10, "perh_root"),
/src/sys/external/gpl2/dts/dist/arch/riscv/boot/dts/starfive/
jh7110.dtsi	678 clocks = <&syscrg JH7110_SYSCLK_UART5_CORE>,

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