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    Searched refs:JZ_TC_TECR (Results 1 - 3 of 3) sorted by relevancy

/src/sys/arch/evbmips/ingenic/
clock.c	99 writereg(JZ_TC_TECR, TESR_TCST5); /* disable timer 5 */
machdep.c	113 writereg(JZ_TC_TECR, TESR_OST);
/src/sys/arch/mips/ingenic/
ingenic_regs.h	75 #define JZ_TC_TECR 0x10002018 /* TC enable clear reg. */

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