1 /* $NetBSD: pmap_68k.h,v 1.22 2026/07/16 14:15:15 thorpej Exp $ */ 2 3 /*- 4 * Copyright (c) 2025 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /* 33 * Copyright (c) 1987 Carnegie-Mellon University 34 * Copyright (c) 1991, 1993 35 * The Regents of the University of California. All rights reserved. 36 * 37 * This code is derived from software contributed to Berkeley by 38 * the Systems Programming Group of the University of Utah Computer 39 * Science Department. 40 * 41 * Redistribution and use in source and binary forms, with or without 42 * modification, are permitted provided that the following conditions 43 * are met: 44 * 1. Redistributions of source code must retain the above copyright 45 * notice, this list of conditions and the following disclaimer. 46 * 2. Redistributions in binary form must reproduce the above copyright 47 * notice, this list of conditions and the following disclaimer in the 48 * documentation and/or other materials provided with the distribution. 49 * 3. Neither the name of the University nor the names of its contributors 50 * may be used to endorse or promote products derived from this software 51 * without specific prior written permission. 52 * 53 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 54 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 55 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 56 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 57 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 58 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 59 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 60 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 61 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 62 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 63 * SUCH DAMAGE. 64 * 65 * @(#)pmap.h 8.1 (Berkeley) 6/10/93 66 */ 67 68 #ifndef _M68K_PMAP_68K_H_ 69 #define _M68K_PMAP_68K_H_ 70 71 #if defined(_KERNEL) 72 73 #if !defined(_MODULE) 74 75 #include <sys/rbtree.h> 76 #include <sys/queue.h> 77 78 #include <m68k/mmu_51.h> 79 #include <m68k/mmu_40.h> 80 81 #include <sys/kcore.h> 82 #include <m68k/kcore.h> 83 84 typedef unsigned int pt_entry_t; 85 86 #define NPTEPG (PAGE_SIZE / (sizeof(pt_entry_t))) 87 88 TAILQ_HEAD(pmap_ptpage_list, pmap_ptpage); 89 LIST_HEAD(pmap_pv_list, pv_entry); 90 91 struct pmap { 92 struct pmap_table *pm_lev1map; /* level 1 table */ 93 paddr_t pm_lev1pa; /* PA of level 1 table */ 94 uint16_t pm_refcnt; /* reference count */ 95 uint16_t pm_busy; /* "busy" (currently loaded in 96 to MMU, or involved in 97 some pmap operation) count */ 98 99 struct pmap_table *pm_pt_cache; /* most recently used leaf table */ 100 101 /* Red-Black tree that contains the active tables. */ 102 struct rb_tree pm_tables; /* lev1map not in here */ 103 104 /* Page table pages for segment and leaf tables. */ 105 struct pmap_ptpage_list pm_ptpages[2]; 106 107 struct pmap_pv_list pm_pvlist; /* all associated P->V entries */ 108 109 struct pmap_statistics pm_stats;/* statistics */ 110 }; 111 112 /* 113 * One entry per P->V mapping of a managed page. 114 * 115 * N.B. We want to keep this structure's size to be a multiple of 116 * 8; we want to align them to 8 bytes in order to be able to use 117 * the lower 3 bits of the pv_entry list head for page attributes. 118 */ 119 struct pv_entry { 120 /* 0*/ struct pv_entry *pv_next; /* link on page list */ 121 /* 4*/ LIST_ENTRY(pv_entry) pv_pmlist; /* link on pmap list */ 122 /*12*/ pmap_t pv_pmap; /* pmap that contains mapping */ 123 /*16*/ vaddr_t pv_vf; /* virtual address + flags */ 124 /*20*/ struct pmap_table *pv_pt; /* table that contains the PTE */ 125 /*24*/ 126 }; 127 128 /* Upper bits of pv_vf contain the virtual address */ 129 #define PV_VA(pv) ((pv)->pv_vf & ~PAGE_MASK) 130 131 /* Lower bits of pv_vf contain flags */ 132 #define PV_F_CI_VAC __BIT(0) /* mapping CI due to VAC alias */ 133 #define PV_F_CI_USR __BIT(1) /* mapping CI due to user request */ 134 135 /* 136 * This describes an individual table used by the MMU. Depending on 137 * the MMU configuration, there may be more than one table per physical 138 * page. 139 * 140 * For leaf (page) and inner segment tables, pt_st points to the 141 * segment table one level up in the tree that maps it, and pt_stidx 142 * is the index into that segment table. pt_st also serves as a 143 * proxy for whether or not the table has been inserted into the 144 * table lookup tree. For the level-1 table, pt_st is NULL and 145 * that table is not inserted into the lookup tree. 146 */ 147 struct pmap_table { 148 struct pmap_ptpage *pt_ptpage; 149 pt_entry_t *pt_entries; 150 struct pmap_table *pt_st; 151 unsigned short pt_holdcnt; 152 unsigned short pt_stidx; 153 unsigned int pt_key; 154 union { 155 LIST_ENTRY(pmap_table) pt_freelist; 156 struct rb_node pt_node; 157 }; 158 }; 159 160 /* 161 * This describes a page table page, which contains one or more MMU tables. 162 * It's variable length, and the table descriptors are allocated along with. 163 */ 164 struct pmap_ptpage { 165 TAILQ_ENTRY(pmap_ptpage) ptp_list; 166 LIST_HEAD(, pmap_table) ptp_freelist; 167 struct vm_page *ptp_pg; 168 unsigned int ptp_vpagenum : 23, 169 ptp_freecnt : 8, 170 ptp_segtab : 1; 171 struct pmap_table ptp_tables[]; 172 }; 173 174 /* 175 * This structure describes regions to be statically allocated / mapped by 176 * pmap_boostrap1(). This is used for the fixed regions that everyone 177 * gets (kernel text / data / bss / symbols, lwp0 u-area, msgbuf address, 178 * etc.) as well as any additional static regions (device areas, etc.) that 179 * need to be mapped (with KVA space) or reserved (because they're mapped 180 * with TT registers). 181 * 182 * Some notes: 183 * 184 * - Virtual addresses are allocated and stored in the variable pointed 185 * to by pmbm_vaddr_ptr, **unless** the PMBM_F_KEEPOUT or PMBM_F_FIXEDVA 186 * flags are set, in which case the pmbm_vaddr field indicates a range 187 * that kernel virtual space should keep out of (PMBM_F_KEEPOUT - usually 188 * because it's mapped by Transparent Translation registers) or that is 189 * used for a fixed-VA special mapping (PMBM_F_FIXEDVA). 190 * 191 * - If the PMBM_F_VAONLY flag is set, only VA space will be allocated, 192 * no mapping will be entered in the space. 193 * 194 * N.B. PMBM_F_KEEPOUT VA regions are assumed to lie beyond the normal 195 * kernel virtual address space. The maximum kernel virtual address will 196 * be clamped to ensure that it never grows into the lowest of these regions. 197 * 198 * pmap_bootstrap1() makes no effort to ensure there are PTs backing any 199 * PMBM_F_FIXEDVA range. It is assumed that any fixed VA mapping will 200 * occur within an already-provisioned VA range. 201 * 202 * All regions will be rounded / aligned to page boundaries. 203 * 204 * This list is terminated by placing a (vaddr_t)-1 in the pmbm_vaddr 205 * field. 206 * 207 * N.B. IF YOU CHANGE THIS STRUCTURE, AUDIT ALL DECLS OF machine_bootmap[]. 208 */ 209 struct pmap_bootmap { 210 union { 211 vaddr_t pmbm_vaddr; 212 vaddr_t * pmbm_vaddr_ptr; 213 }; 214 paddr_t pmbm_paddr; 215 size_t pmbm_size; 216 int pmbm_flags; 217 }; 218 219 #define PMBM_F_VAONLY __BIT(0) 220 #define PMBM_F_FIXEDVA __BIT(1) 221 #define PMBM_F_KEEPOUT __BIT(2) 222 #define PMBM_F_CI __BIT(3) /* cache-inhibited mapping */ 223 #define PMBM_F_CWT __BIT(4) /* write-through cacheable mapping */ 224 #define PMBM_F_RO __BIT(5) /* read-only mapping */ 225 226 /* 227 * Abstract definitions for PTE bits / fields. C code will compile-time- 228 * assert the equivalencies that we assume. 229 * 230 * N.B. assumes exclusive use of short descriptors on 68851. 231 */ 232 #define PTE_VALID PTE40_RESIDENT /* == DT51_PAGE */ 233 #define PTE_WP PTE40_W /* == PTE51_WP */ 234 #define PTE_M PTE40_M /* == PTE51_M */ 235 #define PTE_U PTE40_U /* == PTE51_U */ 236 #define PTE_PVLIST PTE40_G /* unused on '51, don't use PFLUSHxN */ 237 #define PTE_WIRED PTE40_UR /* unused on '51 */ 238 239 /* 240 * PTE40_CM overlaps with PTE51_CI and PTE51_L (which we don't use). 241 */ 242 #define PTE_CMASK PTE40_CM 243 244 /* 245 * Critical bits that, when changed (see pmap_changebit()), require 246 * invalidation of the ATC. 247 */ 248 #define PTE_CRIT_BITS (PTE_WP | PTE_CMASK) 249 250 /* 251 * Root Pointer attributes for Supervisor and User modes. 252 * 253 * Supervisor: 254 * - No index limit (Lower limit == 0) 255 * - Points to Short format descriptor table. 256 * - Shared Globally 257 * 258 * User: 259 * - No index limit (Lower limit == 0) 260 * - Points to Short format descriptor table. 261 */ 262 #define MMU51_SRP_BITS (DTE51_LOWER | DTE51_SG | DT51_SHORT) 263 #define MMU51_CRP_BITS (DTE51_LOWER | DT51_SHORT) 264 265 /* 266 * Our abstract definition of a "segment" is "that which points to the 267 * leaf tables". On the 2-level configuration, that's the level 1 table, 268 * and on the 3-level configuration, that's the level 2 table. 269 * 270 * This is the logical address layout: 271 * 272 * 2-level 4KB/page: l1,l2,page == 10,10,12 (HP MMU compatible) 273 * 2-level 8KB/page: l1,l2,page == 8,11,13 274 * 3-level 4KB/page: l1,l2,l3,page == 7,7,6,12 275 * 3-level 8KB/page: l1,l2,l3,page == 7,7,5,13 276 * 277 * The 2-level l2 size is chosen per the number of page table entries 278 * per page, to use one whole page for PTEs per one segment table entry. 279 * 280 * The 3-level layout is defined by the 68040/68060 hardware, and is not 281 * configurable (other than chosen page size). If '851 / '030 chooses 282 * to use the 3-level layout, it is specifically configured to be compatible 283 * with the 68040. 284 */ 285 /* 8KB / 4KB */ 286 #define LA2L_L2_NBITS (PAGE_SHIFT - 2) /* 11 / 10 */ 287 #define LA2L_L2_COUNT __BIT(LA2L_L2_NBITS) /* 2048 / 1024 */ 288 #define LA2L_L2_SHIFT PAGE_SHIFT /* 13 / 12 */ 289 #define LA2L_L1_NBITS (32 - LA2L_L2_NBITS - PAGE_SHIFT)/* 8 / 10 */ 290 #define LA2L_L1_COUNT __BIT(LA2L_L1_NBITS) /* 256 / 1024 */ 291 #define LA2L_L1_SHIFT (LA2L_L2_NBITS + PAGE_SHIFT) /* 24 / 22 */ 292 293 #define LA2L_L1_MASK (__BITS(0,(LA2L_L1_NBITS - 1)) << LA2L_L1_SHIFT) 294 #define LA2L_L2_MASK (__BITS(0,(LA2L_L2_NBITS - 1)) << LA2L_L2_SHIFT) 295 296 #define LA2L_RI(va) __SHIFTOUT((va), LA2L_L1_MASK) /* root index */ 297 #define LA2L_PGI(va) __SHIFTOUT((va), LA2L_L2_MASK) /* page index */ 298 299 #define MMU51_TCR_BITS (TCR51_E | TCR51_SRE | \ 300 __SHIFTIN(PAGE_SHIFT, TCR51_PS) | \ 301 __SHIFTIN(LA2L_L1_NBITS, TCR51_TIA) | \ 302 __SHIFTIN(LA2L_L2_NBITS, TCR51_TIB)) 303 304 #define MMU51_3L_TCR_BITS (TCR51_E | TCR51_SRE | \ 305 __SHIFTIN(PAGE_SHIFT, TCR51_PS) | \ 306 __SHIFTIN(LA40_L1_NBITS, TCR51_TIA) | \ 307 __SHIFTIN(LA40_L2_NBITS, TCR51_TIB) | \ 308 __SHIFTIN(LA40_L3_NBITS, TCR51_TIC)) 309 310 #define MMU40_TCR_BITS (TCR40_E | \ 311 __SHIFTIN(PAGE_SHIFT - 12, TCR40_P)) 312 313 /* SEG1SHIFT3L is for the "upper" segment on the 3-level configuration */ 314 #define SEGSHIFT2L (LA2L_L1_SHIFT) /* 24 / 22 */ 315 #define SEGSHIFT3L (LA40_L2_SHIFT) /* 18 / 18 */ 316 #define SEG1SHIFT3L (LA40_L1_SHIFT) /* 25 / 25 */ 317 318 /* NBSEG13L is for the "upper" segment on the 3-level configuration */ 319 #define NBSEG2L __BIT(SEGSHIFT2L) 320 #define NBSEG3L __BIT(SEGSHIFT3L) 321 #define NBSEG13L __BIT(SEG1SHIFT3L) 322 323 #define SEGOFSET2L (NBSEG2L - 1) 324 #define SEGOFSET3L (NBSEG3L - 1) 325 #define SEG1OFSET3L (NBSEG13L - 1) 326 327 #define pmap_trunc_seg_2L(va) (((vaddr_t)(va)) & ~SEGOFSET2L) 328 #define pmap_round_seg_2L(va) (pmap_trunc_seg_2L((vaddr_t)(va) + SEGOFSET2L)) 329 #define pmap_seg_offset_2L(va) (((vaddr_t)(va)) & SEGOFSET2L) 330 331 #define pmap_trunc_seg_3L(va) (((vaddr_t)(va)) & ~SEGOFSET3L) 332 #define pmap_round_seg_3L(va) (pmap_trunc_seg_3L((vaddr_t)(va) + SEGOFSET3L)) 333 #define pmap_seg_offset_3L(va) (((vaddr_t)(va)) & SEGOFSET3L) 334 335 #define pmap_trunc_seg1_3L(va) (((vaddr_t)(va)) & ~SEG1OFSET3L) 336 #define pmap_round_seg1_3L(va) (pmap_trunc_seg1_3L((vaddr_t)(va)+ SEG1OFSET3L)) 337 #define pmap_seg1_offset_3L(va) (((vaddr_t)(va)) & SEG1OFSET3L) 338 339 /* 340 * pmap-specific data store in the vm_page structure. 341 * 342 * We keep the U/M attrs in the lower 2 bits of the list head 343 * pointer. This is possible because both the U and M bits are 344 * adjacent; we just need to shift them down 3 bit positions. 345 * 346 * Assumes that PV entries will be 4-byte aligned, but the allocator 347 * guarantees this for us. 348 */ 349 #define __HAVE_VM_PAGE_MD 350 struct vm_page_md { 351 uintptr_t pvh_listx; /* pv_entry list + attrs */ 352 }; 353 354 #define PVH_UM_SHIFT 3 355 #define PVH_UM_MASK __BITS(0,1) 356 #define PVH_CI __BIT(2) 357 #define PVH_ATTR_MASK (PVH_UM_MASK | PVH_CI) 358 #define PVH_PV_MASK (~PVH_ATTR_MASK) 359 360 #define VM_MDPAGE_INIT(pg) \ 361 do { \ 362 (pg)->mdpage.pvh_listx = 0; \ 363 } while (/*CONSTCOND*/0) 364 365 #define VM_MDPAGE_PVS(pg) \ 366 ((struct pv_entry *)((pg)->mdpage.pvh_listx & (uintptr_t)PVH_PV_MASK)) 367 368 #define VM_MDPAGE_HEAD_PVP(pg) \ 369 ((struct pv_entry **)&(pg)->mdpage.pvh_listx) 370 371 #define VM_MDPAGE_SETPVP(pvp, pv) \ 372 do { \ 373 /* \ 374 * The page attributes are in the lower two bits of \ 375 * the first PV pointer. Rather than comparing the \ 376 * address and branching, we just always preserve what \ 377 * might be there (either the attribute bits or zero \ 378 * bits). \ 379 */ \ 380 *(pvp) = (struct pv_entry *) \ 381 ((uintptr_t)(pv) | \ 382 (((uintptr_t)(*(pvp))) & (uintptr_t)PVH_ATTR_MASK));\ 383 } while (/*CONSTCOND*/0) 384 385 #define VM_MDPAGE_UM(pg) \ 386 (((pg)->mdpage.pvh_listx & PVH_UM_MASK) << PVH_UM_SHIFT) 387 388 #define VM_MDPAGE_ADD_UM(pg, a) \ 389 do { \ 390 (pg)->mdpage.pvh_listx |= \ 391 ((a) >> PVH_UM_SHIFT) & PVH_UM_MASK; \ 392 } while (/*CONSTCOND*/0) 393 394 #define VM_MDPAGE_SET_UM(pg, v) \ 395 do { \ 396 (pg)->mdpage.pvh_listx = \ 397 ((pg)->mdpage.pvh_listx & ~PVH_UM_MASK) | \ 398 (((v) >> PVH_UM_SHIFT) & PVH_UM_MASK); \ 399 } while (/*CONSTCOND*/0) 400 401 #define VM_MDPAGE_SET_CI(pg) \ 402 do { \ 403 (pg)->mdpage.pvh_listx |= PVH_CI; \ 404 } while (/*CONSTCOND*/0) 405 406 #define VM_MDPAGE_CLR_CI(pg) \ 407 do { \ 408 (pg)->mdpage.pvh_listx &= ~PVH_CI; \ 409 } while (/*CONSTCOND*/0) 410 411 #define VM_MDPAGE_CI_P(pg) \ 412 ((pg)->mdpage.pvh_listx & PVH_CI) 413 414 #define pmap_copy(dp, sp, da, l, sa) __nothing 415 416 #define pmap_resident_count(pmap) ((pmap)->pm_stats.resident_count) 417 #define pmap_wired_count(pmap) ((pmap)->pm_stats.wired_count) 418 419 #define PMAP_GROWKERNEL /* enable pmap_growkernel() */ 420 421 void pmap_procwr(struct proc *, vaddr_t, size_t); 422 #define PMAP_NEED_PROCWR 423 424 /* 425 * pmap_bootstrap1() is called before the MMU is turned on. 426 * pmap_bootstrap2() is called after. 427 */ 428 paddr_t pmap_bootstrap1(paddr_t/*nextpa*/, paddr_t/*reloff*/); 429 void * pmap_bootstrap2(void); 430 431 /* 432 * Variant of pmap_extract() that returns additional information about 433 * the mapping. Used by bus_dma(9). 434 */ 435 bool pmap_extract_info(pmap_t, vaddr_t, paddr_t *, int *); 436 437 /* 438 * Functions to determine if a VA/PA range is a static mapping created 439 * by pmap_bootstrap1(), for the benefit of bus_space(9). 440 */ 441 extern struct pmap_bootmap machine_bootmap[]; 442 bool pmap_pa_has_static_mapping(paddr_t, size_t, vm_prot_t, 443 vaddr_t *, int *); 444 bool pmap_va_is_static_mapping(vaddr_t, size_t); 445 446 /* Kernel debugger support functions. */ 447 struct pmap_db_write_text_context { 448 vaddr_t pgva; 449 pt_entry_t * ptep; 450 pt_entry_t opte; 451 }; 452 bool pmap_db_write_text_enter(vaddr_t, struct pmap_db_write_text_context *); 453 void pmap_db_write_text_exit(struct pmap_db_write_text_context *); 454 455 /* 456 * Functions exported for compatibility with the Hibler pmap, where 457 * these are needed by other shared m68k code. 458 * 459 * XXX Clean this up eventually. 460 */ 461 paddr_t vtophys(vaddr_t); 462 463 extern char * vmmap; 464 extern void * msgbufaddr; 465 466 /* Support functions for HP MMU. */ 467 void pmap_init_vac(size_t); 468 void pmap_prefer(vaddr_t, vaddr_t *, int); 469 /* PMAP_PREFER() defined in <machine/pmap.h> on machines were it's needed. */ 470 471 /* 472 * pmap hook for trap()'s page fault handler. We don't need to 473 * do anything special, so it just goes to uvm_fault(). 474 */ 475 #define pmap_fault(m, v, t) uvm_fault((m), (v), (t)) 476 477 /* Kernel crash dump support. */ 478 phys_ram_seg_t * pmap_init_kcore_hdr(cpu_kcore_hdr_t *); 479 480 /* 481 * pmap_bootstrap1() may need to relocate global references, and perform 482 * VA <-> PA conversions. These macros facilitate these conversions, and 483 * can be overridden in <machine/pmap.h> before including <m68k/pmap_68k.h> 484 * if needed. 485 * 486 * The first two macros are specifically for converting addresses within 487 * the confines of pmap_bootstrap1(). We may be running with the MMU off 488 * (and either VA==PA or VA!=PA) or with the MMU on with some mappings. 489 * The default ones are suitable for the "MMU off" case with the relocation 490 * offset passed in the "reloff" variable. 491 * 492 * - PMAP_BOOTSTRAP_RELOC_GLOB() -- relocate a global reference in order 493 * to access it during bootstrap. 494 * 495 * - PMAP_BOOTSTRAP_RELOC_PA() -- relocate a physical address in order to 496 * access it during bootstrap. 497 * 498 * The next two macros are intended to convert kernel virtual <-> physical 499 * addresses that will be used in the context of the running kernel once 500 * the MMU is enabled and running on the kernel's ultimate mappings: 501 * 502 * - PMAP_BOOTSTRAP_VA_TO_PA() -- convert a kernel virtual address to 503 * a physical address using linear relocation. 504 * 505 * - PMAP_BOOTSTRAP_PA_TO_VA() -- and vice versa. 506 */ 507 #ifndef PMAP_BOOTSTRAP_RELOC_GLOB 508 #define PMAP_BOOTSTRAP_RELOC_GLOB(va) \ 509 ((((vaddr_t)(va)) - VM_MIN_KERNEL_ADDRESS) + reloff) 510 #endif 511 512 #ifndef PMAP_BOOTSTRAP_RELOC_PA 513 #define PMAP_BOOTSTRAP_RELOC_PA(pa) \ 514 ((vaddr_t)(pa)) 515 #endif 516 517 #ifndef PMAP_BOOTSTRAP_VA_TO_PA 518 #define PMAP_BOOTSTRAP_VA_TO_PA(va) \ 519 ((((vaddr_t)(va)) - VM_MIN_KERNEL_ADDRESS) + reloff) 520 #endif 521 522 #ifndef PMAP_BOOTSTRAP_PA_TO_VA 523 #define PMAP_BOOTSTRAP_PA_TO_VA(pa) \ 524 (VM_MIN_KERNEL_ADDRESS + (((paddr_t)(pa)) - reloff)) 525 #endif 526 527 #endif /* ! _MODULE */ 528 529 /* 530 * Some pmap(9) API macros should be defined here for module(7). 531 * Luckily, all m68k pmap implementations behave this way. (see PR/54869) 532 */ 533 #define pmap_update(pmap) __nothing 534 535 #endif /* _KERNEL */ 536 537 #endif /* _M68K_PMAP_68K_H_ */ 538
Indexes created Tue Aug 11 00:25:38 UTC 2026