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      1 /*	$NetBSD: mt2701-larb-port.h,v 1.1.1.3 2021/11/07 16:49:56 jmcneill Exp $	*/
      2 
      3 /* SPDX-License-Identifier: GPL-2.0-only */
      4 /*
      5  * Copyright (c) 2015 MediaTek Inc.
      6  * Author: Honghui Zhang <honghui.zhang (at) mediatek.com>
      7  */
      8 
      9 #ifndef _DT_BINDINGS_MEMORY_MT2701_LARB_PORT_H_
     10 #define _DT_BINDINGS_MEMORY_MT2701_LARB_PORT_H_
     11 
     12 /*
     13  * Mediatek m4u generation 1 such as mt2701 has flat m4u port numbers,
     14  * the first port's id for larb[N] would be the last port's id of larb[N - 1]
     15  * plus one while larb[0]'s first port number is 0. The definition of
     16  * MT2701_M4U_ID_LARBx is following HW register spec.
     17  * But m4u generation 2 like mt8173 have different port number, it use fixed
     18  * offset for each larb, the first port's id for larb[N] would be (N * 32).
     19  */
     20 #define LARB0_PORT_OFFSET		0
     21 #define LARB1_PORT_OFFSET		11
     22 #define LARB2_PORT_OFFSET		21
     23 #define LARB3_PORT_OFFSET		44
     24 
     25 #define MT2701_M4U_ID_LARB0(port)	((port) + LARB0_PORT_OFFSET)
     26 #define MT2701_M4U_ID_LARB1(port)	((port) + LARB1_PORT_OFFSET)
     27 #define MT2701_M4U_ID_LARB2(port)	((port) + LARB2_PORT_OFFSET)
     28 
     29 /* Port define for larb0 */
     30 #define MT2701_M4U_PORT_DISP_OVL_0		MT2701_M4U_ID_LARB0(0)
     31 #define MT2701_M4U_PORT_DISP_RDMA1		MT2701_M4U_ID_LARB0(1)
     32 #define MT2701_M4U_PORT_DISP_RDMA		MT2701_M4U_ID_LARB0(2)
     33 #define MT2701_M4U_PORT_DISP_WDMA		MT2701_M4U_ID_LARB0(3)
     34 #define MT2701_M4U_PORT_MM_CMDQ			MT2701_M4U_ID_LARB0(4)
     35 #define MT2701_M4U_PORT_MDP_RDMA		MT2701_M4U_ID_LARB0(5)
     36 #define MT2701_M4U_PORT_MDP_WDMA		MT2701_M4U_ID_LARB0(6)
     37 #define MT2701_M4U_PORT_MDP_ROTO		MT2701_M4U_ID_LARB0(7)
     38 #define MT2701_M4U_PORT_MDP_ROTCO		MT2701_M4U_ID_LARB0(8)
     39 #define MT2701_M4U_PORT_MDP_ROTVO		MT2701_M4U_ID_LARB0(9)
     40 #define MT2701_M4U_PORT_MDP_RDMA1		MT2701_M4U_ID_LARB0(10)
     41 
     42 /* Port define for larb1 */
     43 #define MT2701_M4U_PORT_VDEC_MC_EXT		MT2701_M4U_ID_LARB1(0)
     44 #define MT2701_M4U_PORT_VDEC_PP_EXT		MT2701_M4U_ID_LARB1(1)
     45 #define MT2701_M4U_PORT_VDEC_PPWRAP_EXT		MT2701_M4U_ID_LARB1(2)
     46 #define MT2701_M4U_PORT_VDEC_AVC_MV_EXT		MT2701_M4U_ID_LARB1(3)
     47 #define MT2701_M4U_PORT_VDEC_PRED_RD_EXT	MT2701_M4U_ID_LARB1(4)
     48 #define MT2701_M4U_PORT_VDEC_PRED_WR_EXT	MT2701_M4U_ID_LARB1(5)
     49 #define MT2701_M4U_PORT_VDEC_VLD_EXT		MT2701_M4U_ID_LARB1(6)
     50 #define MT2701_M4U_PORT_VDEC_VLD2_EXT		MT2701_M4U_ID_LARB1(7)
     51 #define MT2701_M4U_PORT_VDEC_TILE_EXT		MT2701_M4U_ID_LARB1(8)
     52 #define MT2701_M4U_PORT_VDEC_IMG_RESZ_EXT	MT2701_M4U_ID_LARB1(9)
     53 
     54 /* Port define for larb2 */
     55 #define MT2701_M4U_PORT_VENC_RCPU		MT2701_M4U_ID_LARB2(0)
     56 #define MT2701_M4U_PORT_VENC_REC_FRM		MT2701_M4U_ID_LARB2(1)
     57 #define MT2701_M4U_PORT_VENC_BSDMA		MT2701_M4U_ID_LARB2(2)
     58 #define MT2701_M4U_PORT_JPGENC_RDMA		MT2701_M4U_ID_LARB2(3)
     59 #define MT2701_M4U_PORT_VENC_LT_RCPU		MT2701_M4U_ID_LARB2(4)
     60 #define MT2701_M4U_PORT_VENC_LT_REC_FRM		MT2701_M4U_ID_LARB2(5)
     61 #define MT2701_M4U_PORT_VENC_LT_BSDMA		MT2701_M4U_ID_LARB2(6)
     62 #define MT2701_M4U_PORT_JPGDEC_BSDMA		MT2701_M4U_ID_LARB2(7)
     63 #define MT2701_M4U_PORT_VENC_SV_COMV		MT2701_M4U_ID_LARB2(8)
     64 #define MT2701_M4U_PORT_VENC_RD_COMV		MT2701_M4U_ID_LARB2(9)
     65 #define MT2701_M4U_PORT_JPGENC_BSDMA		MT2701_M4U_ID_LARB2(10)
     66 #define MT2701_M4U_PORT_VENC_CUR_LUMA		MT2701_M4U_ID_LARB2(11)
     67 #define MT2701_M4U_PORT_VENC_CUR_CHROMA		MT2701_M4U_ID_LARB2(12)
     68 #define MT2701_M4U_PORT_VENC_REF_LUMA		MT2701_M4U_ID_LARB2(13)
     69 #define MT2701_M4U_PORT_VENC_REF_CHROMA		MT2701_M4U_ID_LARB2(14)
     70 #define MT2701_M4U_PORT_IMG_RESZ		MT2701_M4U_ID_LARB2(15)
     71 #define MT2701_M4U_PORT_VENC_LT_SV_COMV		MT2701_M4U_ID_LARB2(16)
     72 #define MT2701_M4U_PORT_VENC_LT_RD_COMV		MT2701_M4U_ID_LARB2(17)
     73 #define MT2701_M4U_PORT_VENC_LT_CUR_LUMA	MT2701_M4U_ID_LARB2(18)
     74 #define MT2701_M4U_PORT_VENC_LT_CUR_CHROMA	MT2701_M4U_ID_LARB2(19)
     75 #define MT2701_M4U_PORT_VENC_LT_REF_LUMA	MT2701_M4U_ID_LARB2(20)
     76 #define MT2701_M4U_PORT_VENC_LT_REF_CHROMA	MT2701_M4U_ID_LARB2(21)
     77 #define MT2701_M4U_PORT_JPGDEC_WDMA		MT2701_M4U_ID_LARB2(22)
     78 
     79 #endif
     80