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    Searched refs:LEVEL0_MPLL_DIV_EN (Results 1 - 2 of 2) sorted by relevancy

/src/sys/external/bsd/drm2/dist/drm/radeon/
rv6xxd.h	87 # define LEVEL0_MPLL_DIV_EN (1 << 28)
radeon_rv6xx_dpm.c	379 LEVEL0_MPLL_DIV_EN, ~LEVEL0_MPLL_DIV_EN); 381 WREG32_P(MPLL_FREQ_LEVEL_0 + (index * 4), 0, ~LEVEL0_MPLL_DIV_EN);

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Indexes created Sat Oct 11 19:10:01 GMT 2025