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    Searched refs:LEVEL0_MPLL_POST_DIV_MASK (Results 1 - 2 of 2) sorted by relevancy

/src/sys/external/bsd/drm2/dist/drm/radeon/
rv6xxd.h	82 # define LEVEL0_MPLL_POST_DIV_MASK (0xff << 0)
radeon_rv6xx_dpm.c	388 LEVEL0_MPLL_POST_DIV(divider), ~LEVEL0_MPLL_POST_DIV_MASK);

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