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    Searched refs:LHSReg (Results 1 - 8 of 8) sorted by relevancy

  /src/external/gpl3/gdb.old/dist/sim/arm/
armemu.h 318 #define LHSReg (BITS (16, 19))
325 #define LHS ((LHSReg == 15) ? (state->Reg[15] & 0xFFFFFFFC): (state->Reg[LHSReg]))
327 #define LHS (state->Reg[LHSReg])
330 #define LHS ((LHSReg == 15) ? R15PC : (state->Reg[LHSReg]))
356 #define LSBase state->Reg[LHSReg]
369 #define LSMBaseFirst ((LHSReg == 0 && BIT (0)) || \
370 (BIT (LHSReg) && BITS (0, LHSReg - 1) == 0)
    [all...]
armsupp.c 569 int base = state->Reg[LHSReg];
573 if (LHSReg == 15)
848 int base = state->Reg[LHSReg];
852 if (LHSReg == 15)
1118 srcN = LHSReg + (BIT (7) << 4);
1124 srcN = (LHSReg << 1) + BIT (7);
armemu.c 2264 else if ((BITS (0, 11) == 0) && (LHSReg == 15))
2569 else if ((BITS (0, 11) == 0) && (LHSReg == 15))
4399 else if (DESTReg == 15 || LHSReg == 15)
5221 return (DESTReg != LHSReg);
5251 return (DESTReg != LHSReg);
5282 return (DESTReg != LHSReg);
5313 addr_reg = LHSReg;
5421 addr_reg = LHSReg;
5613 if (BIT (21) && LHSReg != 15)
5656 if (BIT (21) && LHSReg != 15
    [all...]
  /src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/
AArch64FastISel.cpp 204 unsigned emitAddSub_rr(bool UseAdd, MVT RetVT, unsigned LHSReg,
207 unsigned emitAddSub_ri(bool UseAdd, MVT RetVT, unsigned LHSReg,
210 unsigned emitAddSub_rs(bool UseAdd, MVT RetVT, unsigned LHSReg,
214 unsigned emitAddSub_rx(bool UseAdd, MVT RetVT, unsigned LHSReg,
223 bool emitICmp_ri(MVT RetVT, unsigned LHSReg, uint64_t Imm);
240 unsigned emitSubs_rr(MVT RetVT, unsigned LHSReg, unsigned RHSReg,
242 unsigned emitSubs_rs(MVT RetVT, unsigned LHSReg, unsigned RHSReg,
247 unsigned emitLogicalOp_ri(unsigned ISDOpc, MVT RetVT, unsigned LHSReg,
249 unsigned emitLogicalOp_rs(unsigned ISDOpc, MVT RetVT, unsigned LHSReg,
251 unsigned emitAnd_ri(MVT RetVT, unsigned LHSReg, uint64_t Imm)
    [all...]
  /src/external/apache2/llvm/dist/llvm/lib/Target/ARM/
ARMInstructionSelector.cpp 51 // if \p LHSReg and \p RHSReg are in the relationship defined by \p Cond, or
54 ARMCC::CondCodes Cond, unsigned LHSReg, unsigned RHSReg,
502 unsigned LHSReg, unsigned RHSReg,
505 return MRI.getType(LHSReg) == MRI.getType(RHSReg) &&
506 validReg(MRI, LHSReg, ExpectedSize, ExpectedRegBankID) &&
543 auto LHSReg = MIB.getReg(2);
545 if (!validOpRegPair(MRI, LHSReg, RHSReg, Helper.OperandSize,
555 if (!insertComparison(Helper, I, ResReg, ARMConds.first, LHSReg, RHSReg,
561 if (!insertComparison(Helper, I, IntermediateRes, ARMConds.first, LHSReg,
564 if (!insertComparison(Helper, I, ResReg, ARMConds.second, LHSReg, RHSReg
    [all...]
  /src/external/apache2/llvm/dist/llvm/lib/Target/X86/
X86FastISel.cpp 2142 Register LHSReg = getRegForValue(LHS);
2143 if (!LHSReg || !RHSReg)
2148 Register ResultReg = fastEmitInst_rri(Opc, RC, RHSReg, LHSReg, CC);
2196 Register LHSReg = getRegForValue(LHS);
2200 if (!LHSReg || !RHSReg || !CmpLHSReg || !CmpRHSReg)
2227 ImplicitDefReg, LHSReg);
2248 Register VBlendReg = fastEmitInst_rrr(BlendOpcode, VR128, RHSReg, LHSReg,
2269 Register AndReg = fastEmitInst_rr(Opc[1], VR128, CmpReg, LHSReg);
2339 Register LHSReg = getRegForValue(LHS);
2341 if (!LHSReg || !RHSReg
    [all...]
  /src/external/apache2/llvm/dist/llvm/lib/Target/Mips/
MipsFastISel.cpp 316 unsigned LHSReg = getRegForValue(LHS);
317 if (!LHSReg)
332 emitInst(Opc, ResultReg).addReg(LHSReg).addReg(RHSReg);
  /src/external/apache2/llvm/dist/llvm/lib/CodeGen/GlobalISel/
CombinerHelper.cpp 2877 Register LHSReg = MI.getOperand(1).getReg();
2881 if (!MRI.hasOneNonDBGUse(LHSReg) || !MRI.hasOneNonDBGUse(RHSReg))
2885 MachineInstr *LeftHandInst = getDefIgnoringCopies(LHSReg, MRI);

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