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    Searched refs:LMUL (Results 1 - 15 of 15) sorted by relevancy

  /src/external/gpl3/gcc/dist/gcc/config/riscv/
riscv-modes.def 27 /* Encode the ratio of SEW/LMUL into the mask types. There are the following
30 /* Encode the ratio of SEW/LMUL into the mask types.
33 n = SEW/LMUL
81 /* Encode SEW and LMUL into data types.
82 We enforce the constraint LMUL ≥ SEW/ELEN in the implementation.
85 |Modes|LMUL=1 |LMUL=2 |LMUL=4 |LMUL=8 |LMUL=1/2|LMUL=1/4|LMUL=1/8
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riscv.cc 1553 riscv_v_adjust_nunits (machine_mode mode, bool fractional_p, int lmul, int nf)
1561 return nunits_per_chunk / lmul * riscv_vector_chunks * nf;
1563 return nunits_per_chunk * lmul * riscv_vector_chunks * nf;
5177 int LMUL = riscv_v_ext_tuple_mode_p (mode)
5182 int aligned_reg_start = ROUND_UP (arg_reg_start, LMUL);
5189 not been allocated and the first register is aligned with LMUL. */
5190 for (int i = aligned_reg_start; i + nregs - 1 <= arg_reg_end; i += LMUL)
5205 LMUL step to I. */
5206 i += (j / LMUL) * LMUL;
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  /src/external/apache2/llvm/dist/llvm/lib/Target/RISCV/
RISCVISelDAGToDAG.h 101 uint8_t LMUL;
110 uint8_t LMUL;
120 uint8_t LMUL;
129 uint8_t LMUL;
139 uint8_t LMUL;
147 uint8_t LMUL;
155 uint8_t LMUL;
RISCVExpandPseudoInsts.cpp 294 unsigned LMUL = ZvlssegInfo->second;
295 assert(NF * LMUL <= 8 && "Invalid NF/LMUL combinations.");
300 if (LMUL == 2) {
305 } else if (LMUL == 4) {
311 assert(LMUL == 1 && "LMUL must be 1, 2, or 4.");
339 unsigned LMUL = ZvlssegInfo->second;
340 assert(NF * LMUL <= 8 && "Invalid NF/LMUL combinations.")
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RISCVISelDAGToDAG.cpp 111 unsigned NF, RISCVII::VLMUL LMUL) {
112 switch (LMUL) {
114 llvm_unreachable("Invalid LMUL.");
169 RISCVII::VLMUL LMUL = RISCVTargetLowering::getLMUL(VT);
176 SDValue MaskedOff = createTuple(*CurDAG, Regs, NF, LMUL);
186 static_cast<unsigned>(LMUL));
210 RISCVII::VLMUL LMUL = RISCVTargetLowering::getLMUL(VT);
217 SDValue MaskedOff = createTuple(*CurDAG, Regs, NF, LMUL);
227 ScalarSize, static_cast<unsigned>(LMUL));
254 RISCVII::VLMUL LMUL = RISCVTargetLowering::getLMUL(VT)
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RISCVInstrInfo.cpp 135 unsigned LMul = 1;
158 LMul = 1;
163 LMul = 2;
168 LMul = 4;
173 LMul = 1;
178 LMul = 2;
183 LMul = 1;
188 LMul = 2;
193 LMul = 1;
198 LMul = 1
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RISCVISelLowering.cpp 1046 llvm_unreachable("Invalid LMUL.");
1064 unsigned RISCVTargetLowering::getRegClassIDForLMUL(RISCVII::VLMUL LMul) {
1065 switch (LMul) {
1067 llvm_unreachable("Invalid LMUL.");
1083 RISCVII::VLMUL LMUL = getLMUL(VT);
1084 if (LMUL == RISCVII::VLMUL::LMUL_F8 ||
1085 LMUL == RISCVII::VLMUL::LMUL_F4 ||
1086 LMUL == RISCVII::VLMUL::LMUL_F2 ||
1087 LMUL == RISCVII::VLMUL::LMUL_1) {
1092 if (LMUL == RISCVII::VLMUL::LMUL_2)
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  /src/external/apache2/llvm/dist/clang/utils/TableGen/
RISCVVEmitter.cpp 33 // Exponential LMUL
37 // Return the C/C++ string representation of LMUL
60 LMULType LMUL;
209 // Concat BasicType, LMUL and Proto as key
231 /// and LMUL with type transformers). It also record result of type in legal
261 assert(NewLog2LMUL <= 3 && NewLog2LMUL >= -3 && "Bad LMUL number!");
304 : BT(BT), LMUL(LMULType(Log2LMUL)) {
318 // boolean type are encoded the ratio of n (SEW/LMUL)
319 // SEW/LMUL | 1 | 2 | 4 | 8 | 16 | 32 | 64
323 // type\lmul | 1/8 | 1/4 | 1/2 | 1 | 2 | 4 |
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  /src/external/apache2/llvm/dist/llvm/lib/Target/RISCV/MCTargetDesc/
RISCVBaseInfo.h 110 /// \returns the LMUL for the instruction.
317 // Is this a LMUL value that can be encoded into the VTYPE format.
318 inline static bool isValidLMUL(unsigned LMUL, bool Fractional) {
319 return isPowerOf2_32(LMUL) && LMUL <= 8 && (!Fractional || LMUL != 1);
  /src/crypto/external/apache2/openssl/lib/libcrypto/arch/riscv64/
aes-riscv64-zvbb-zvkg-zvkned.S 90 # in a LMUL=4 register group.
91 # n = ((VLEN*LMUL)/(32*4)) = ((VLEN*4)/(32*4))
283 # in a LMUL=4 register group.
284 # n = ((VLEN*LMUL)/(32*4)) = ((VLEN*4)/(32*4))
530 # in a LMUL=4 register group.
531 # n = ((VLEN*LMUL)/(32*4)) = ((VLEN*4)/(32*4))
751 # in a LMUL=4 register group.
752 # n = ((VLEN*LMUL)/(32*4)) = ((VLEN*4)/(32*4))
aes-gcm-riscv64-zvkb-zvkg-zvkned.S 13 # Compute the AES-GCM full-block e32 length for `LMUL=4`. We will handle
14 # the multiple AES-GCM blocks at the same time within `LMUL=4` register.
16 # FULL_BLOCK_LEN32 = (VLEN*LMUL)/(EGW) * (EGW/SEW) = (VLEN*4)/(32*4) * 4
25 ## block number in a LMUL=4 register group.
26 ## n = ((VLEN*LMUL)/(32*4)) = ((VLEN*4)/(32*4))
783 # Compute the AES-GCM full-block e32 length for `LMUL=4`. We will handle
784 # the multiple AES-GCM blocks at the same time within `LMUL=4` register.
786 # FULL_BLOCK_LEN32 = (VLEN*LMUL)/(EGW) * (EGW/SEW) = (VLEN*4)/(32*4) * 4
795 ## block number in a LMUL=4 register group.
796 ## n = ((VLEN*LMUL)/(32*4)) = ((VLEN*4)/(32*4)
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  /src/external/apache2/llvm/dist/llvm/lib/Target/XCore/
XCoreISelLowering.h 58 // Corresponds to LMUL instruction
59 LMUL,
XCoreISelDAGToDAG.cpp 190 case XCoreISD::LMUL: {
XCoreISelLowering.cpp 59 case XCoreISD::LMUL : return "XCoreISD::LMUL";
564 SDValue Hi = DAG.getNode(XCoreISD::LMUL, dl,
1706 case XCoreISD::LMUL: {
1718 return DAG.getNode(XCoreISD::LMUL, dl, DAG.getVTList(VT, VT),
1721 // lmul(x, 0, a, b)
1740 // lmul(x, y, a, b). The high result of lmul will be ignored.
1746 SDValue Ignored = DAG.getNode(XCoreISD::LMUL, dl,
1754 // lmul(x, y, a, b) if all operands are zero-extended. We do thi
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  /src/external/apache2/llvm/dist/clang/lib/CodeGen/
CGDebugInfo.cpp 773 unsigned LMUL;
777 LMUL = 1;
781 LMUL = 64 / FixedSize;
783 LMUL = FixedSize / 64;
786 // Element count = (VLENB / SEW) x LMUL
796 llvm::dwarf::DW_OP_div, llvm::dwarf::DW_OP_constu, LMUL});

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