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    Searched refs:LMul (Results 1 - 4 of 4) sorted by relevancy

  /src/external/apache2/llvm/dist/llvm/lib/Target/RISCV/MCTargetDesc/
RISCVBaseInfo.cpp 109 // 2:0 | vlmul[2:0] | Vector register group multiplier (LMUL) setting
132 llvm_unreachable("Unexpected LMUL value!");
137 unsigned LMul = 1 << static_cast<unsigned>(VLMUL);
138 OS << ",m" << LMul;
144 unsigned LMul = 1 << (8 - static_cast<unsigned>(VLMUL));
145 OS << ",mf" << LMul;
  /src/external/apache2/llvm/dist/llvm/lib/Target/RISCV/
RISCVInstrInfo.cpp 135 unsigned LMul = 1;
158 LMul = 1;
163 LMul = 2;
168 LMul = 4;
173 LMul = 1;
178 LMul = 2;
183 LMul = 1;
188 LMul = 2;
193 LMul = 1;
198 LMul = 1
    [all...]
RISCVISelLowering.h 156 // corresponding full-width LMUL=1 type for the first operand:
472 static unsigned getRegClassIDForLMUL(RISCVII::VLMUL LMul);
RISCVISelLowering.cpp 1046 llvm_unreachable("Invalid LMUL.");
1064 unsigned RISCVTargetLowering::getRegClassIDForLMUL(RISCVII::VLMUL LMul) {
1065 switch (LMul) {
1067 llvm_unreachable("Invalid LMUL.");
1083 RISCVII::VLMUL LMUL = getLMUL(VT);
1084 if (LMUL == RISCVII::VLMUL::LMUL_F8 ||
1085 LMUL == RISCVII::VLMUL::LMUL_F4 ||
1086 LMUL == RISCVII::VLMUL::LMUL_F2 ||
1087 LMUL == RISCVII::VLMUL::LMUL_1) {
1092 if (LMUL == RISCVII::VLMUL::LMUL_2)
    [all...]

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