| /src/sys/arch/evbarm/lubbock/ |
| sm_obio_space_asm.S | 50 add r1, r1, r2, LSL #2
53 orr r0, r0, r2, LSL #8
62 add r1, r1, r2, LSL #2
73 add r0, r1, r2, LSL #2
82 orr r1, r1, lr, LSL #8
95 add r0, r1, r2, LSL #2
122 ldrbeq r0, [r1, r2, LSL #2]
127 add r1, r1, r2, LSL #2
140 strbeq r3, [r1, r2, LSL #2]
145 mov r3, r3, LSL #
[all...] |
| /src/sys/external/bsd/gnu-efi/dist/lib/arm/ |
| div.S | 70 subcs r0, r0, r1, LSL #7
73 subcs r0, r0, r1, LSL #6
76 subcs r0, r0, r1, LSL #5
79 subcs r0, r0, r1, LSL #4
83 subcs r0, r0, r1, LSL #3
86 subcs r0, r0, r1, LSL #2
89 subcs r0, r0, r1, LSL #1
106 lsl r1, r1, #6
110 lsl r1, r1, #6
114 lsl r1, r1, #
[all...] |
| /src/sys/arch/arm/xscale/ |
| ixp425_a4x_io.S | 55 ldr r0, [r1, r2, LSL #2]
60 ldr r0, [r1, r2, LSL #2]
62 orr r1, r1, r1, lsl #8
67 ldr r0, [r1, r2, LSL #2]
75 str r3, [r1, r2, LSL #2]
80 orr r0, r0, r0, lsl #8
82 str r3, [r1, r2, LSL #2]
86 str r3, [r1, r2, LSL #2]
93 add r0, r1, r2, lsl #2
105 add r0, r1, r2, lsl #
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/ |
| AArch64ExpandImm.cpp | 82 AArch64_AM::getShifterImm(AArch64_AM::LSL, ShiftAmt) });
97 AArch64_AM::getShifterImm(AArch64_AM::LSL, ShiftAmt) });
228 AArch64_AM::getShifterImm(AArch64_AM::LSL,
237 AArch64_AM::getShifterImm(AArch64_AM::LSL,
269 unsigned Shift = 0; // LSL amount for high bits with MOVZ/MOVN
270 unsigned LastShift = 0; // LSL amount for last MOVK
280 AArch64_AM::getShifterImm(AArch64_AM::LSL, Shift) });
298 AArch64_AM::getShifterImm(AArch64_AM::LSL, Shift) });
371 AArch64_AM::getShifterImm(AArch64_AM::LSL, Shift) });
|
| AArch64ExpandPseudoInsts.cpp | 722 // movk x16, #0xc31a, lsl #48
893 .addImm(AArch64_AM::getShifterImm(AArch64_AM::LSL, 0));
1088 AArch64_AM::getShifterImm(AArch64_AM::LSL, 0),
1093 AArch64_AM::getShifterImm(AArch64_AM::LSL, 0),
|
| AArch64FastISel.cpp | 720 Addr.setExtendType(AArch64_AM::LSL);
802 Addr.setExtendType(AArch64_AM::LSL);
847 Addr.setExtendType(AArch64_AM::LSL);
1057 Addr.getOffsetReg(), AArch64_AM::LSL,
1238 ResultReg = emitAddSub_rs(UseAdd, RetVT, LHSReg, RHSReg, AArch64_AM::LSL,
1252 case Instruction::Shl: ShiftType = AArch64_AM::LSL; break;
1358 .addImm(getShifterImm(AArch64_AM::LSL, ShiftImm));
1720 AArch64_AM::getShifterImm(AArch64_AM::LSL, ShiftImm));
|
| AArch64RegisterInfo.cpp | 560 unsigned Shifter = AArch64_AM::getShifterImm(AArch64_AM::LSL, 0);
|
| /src/sys/arch/evbarm/smdk2xx0/ |
| smdk2410_start.S | 103 add r0,r0,r1,LSL #2
104 add r2,r2,r1,LSL #2
|
| smdk2800_start.S | 75 add r0,r0,r1,LSL #2
76 add r2,r2,r1,LSL #2
|
| /src/external/gpl3/gdb.old/dist/sim/aarch64/ |
| decode.h | 116 LSL = 0,
|
| /src/external/gpl3/gdb/dist/sim/aarch64/ |
| decode.h | 116 LSL = 0,
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/MCTargetDesc/ |
| AArch64AddressingModes.h | 34 LSL = 0,
55 case AArch64_AM::LSL: return "lsl";
76 case 0: return AArch64_AM::LSL;
91 /// shifter: 000 ==> lsl
104 case AArch64_AM::LSL: STEnc = 0; break;
821 // "lsl #0" takes precedence: in practice this only affects "#0, lsl #0".
|
| AArch64MCCodeEmitter.cpp | 265 assert(AArch64_AM::getShiftType(MO1.getImm()) == AArch64_AM::LSL &&
525 assert(AArch64_AM::getShiftType(ShiftOpnd) == AArch64_AM::LSL &&
|
| AArch64InstPrinter.cpp | 124 AsmMnemonic = "lsl";
128 AsmMnemonic = "lsl";
209 // (e.g. :gottprel_g1: is always going to be "lsl #16") so it should not be
232 // domains overlap so they need to be prioritized. The chain is "MOVZ lsl #0 >
233 // MOVZ lsl #N > MOVN lsl #0 > MOVN lsl #N > ORR". The highest instruction
982 // LSL #0 should not be printed.
983 if (AArch64_AM::getShiftType(Val) == AArch64_AM::LSL &&
1012 // UXTW/UXTX as LSL, and if the shift amount is also zero, print nothing a
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/AVR/ |
| AVRISelLowering.h | 38 LSL, ///< Logical shift left.
|
| /src/external/gpl3/binutils/dist/opcodes/ |
| pru-opc.c | 102 DECLARE_FORMAT1_OPCODE (lsl, LSL),
|
| /src/external/gpl3/binutils.old/dist/opcodes/ |
| pru-opc.c | 102 DECLARE_FORMAT1_OPCODE (lsl, LSL),
|
| /src/external/gpl3/gdb.old/dist/opcodes/ |
| pru-opc.c | 102 DECLARE_FORMAT1_OPCODE (lsl, LSL),
|
| /src/external/gpl3/gdb/dist/opcodes/ |
| pru-opc.c | 102 DECLARE_FORMAT1_OPCODE (lsl, LSL),
|
| /src/sys/arch/evbarm/gemini/ |
| gemini_start.S | 175 mov va, va, LSL #2
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/AsmParser/ |
| AArch64AsmParser.cpp | 368 // The default is 'lsl #0' (HasExplicitAmount = false) if no
836 // An ADD/SUB shifter is either 'lsl #0' or 'lsl #12'.
1213 if (isGPR64<RegClassID>() && getShiftExtendType() == AArch64_AM::LSL &&
1266 return (ST == AArch64_AM::LSL || ST == AArch64_AM::LSR ||
1313 ET == AArch64_AM::LSL) &&
1332 ET == AArch64_AM::LSL) &&
1340 return (ET == AArch64_AM::LSL || ET == AArch64_AM::SXTX) &&
1359 // An arithmetic shifter is LSL, LSR, or ASR.
1361 return (ST == AArch64_AM::LSL || ST == AArch64_AM::LSR |
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/Utils/ |
| AArch64BaseInfo.h | 467 LSL,
|
| /src/external/gpl3/gdb.old/dist/sim/arm/ |
| armemu.h | 44 #define LSL 0
|
| armemu.c | 657 /* PKHBT<c> <Rd>,<Rn>,<Rm>{,LSL #<imm>}
4813 case LSL:
4854 case LSL:
4904 case LSL:
4982 case LSL:
5152 case LSL:
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/ |
| HexagonConstPropagation.cpp | 2525 LatticeCell LSL, LSH;
2526 if (!getCell(RL, Inputs, LSL) || !getCell(RH, Inputs, LSH))
2528 if (LSL.isProperty() || LSH.isProperty())
2531 unsigned LN = LSL.size(), HN = LSH.size();
2534 bool Eval = constToInt(LSL.Values[i], LoVs[i]);
|
