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    Searched refs:LShr (Results 1 - 25 of 81) sorted by relevancy

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  /src/external/apache2/llvm/dist/llvm/lib/IR/
ReplaceConstant.cpp 43 case Instruction::LShr:
Instruction.cpp 153 case Instruction::LShr:
386 case LShr: return "lshr";
  /src/external/apache2/llvm/dist/llvm/lib/Target/WebAssembly/
WebAssemblyTargetTransformInfo.cpp 66 case Instruction::LShr:
  /src/external/apache2/llvm/dist/llvm/lib/Target/RISCV/
RISCVTargetTransformInfo.cpp 64 case Instruction::LShr:
  /src/external/apache2/llvm/dist/llvm/include/llvm/IR/
Operator.h 144 OpC == Instruction::LShr;
452 : public ConcreteOperator<PossiblyExactOperator, Instruction::LShr> {
Instruction.h 201 return getOpcode() == Shl || getOpcode() == LShr;
  /src/external/apache2/llvm/dist/llvm/lib/FuzzMutate/
Operations.cpp 27 Ops.push_back(binOpDescriptor(1, Instruction::LShr));
105 case Instruction::LShr:
  /src/external/apache2/llvm/dist/llvm/lib/CodeGen/
InterleavedLoadCombinePass.cpp 129 // %Pa2 = lshr i64 %Pa1, 1
134 // %Pb2 = lshr i64 %Pb1, 1
148 // Pa_2 = %IDX/2 + 1 #1 | lshr 1
155 // Pb_2 = %IDX/2 + 2 #1 | lshr 1
168 LShr,
330 Polynomial &lshr(const APInt &C) { function in class:__anon4196::Polynomial
457 // Remark: Distributing lshr with and arbitrary number n can be expressed as
458 // ((((B + A) lshr 1) lshr 1) ... ) {n times}.
485 pushBOperation(LShr, C)
    [all...]
  /src/external/apache2/llvm/dist/llvm/lib/Transforms/Scalar/
SpeculativeExecution.cpp 224 case Instruction::LShr:
  /src/external/apache2/llvm/dist/llvm/include/llvm/MC/
MCExpr.h 503 LShr, ///< Logical shift right.
605 return create(LShr, LHS, RHS, Ctx);
  /src/external/apache2/llvm/dist/llvm/lib/Target/ARM/
MVELaneInterleavingPass.cpp 231 case Instruction::LShr:
  /src/external/apache2/llvm/dist/llvm/lib/Transforms/Instrumentation/
PoisonChecking.cpp 172 case Instruction::LShr:
353 - Exact flags on ashr/lshr produce poison
  /src/external/apache2/llvm/dist/llvm/lib/Transforms/InstCombine/
InstCombineSimplifyDemanded.cpp 541 APInt DemandedMaskIn(DemandedMask.lshr(ShiftAmt));
588 case Instruction::LShr: {
663 BinaryOperator *LShr = BinaryOperator::CreateLShr(I->getOperand(0),
665 LShr->setIsExact(cast<BinaryOperator>(I)->isExact());
666 return InsertNewInstWith(LShr, *I);
819 APInt DemandedMaskLHS(DemandedMask.lshr(ShiftAmt));
826 RHSKnown.Zero.lshr(BitWidth - ShiftAmt);
828 RHSKnown.One.lshr(BitWidth - ShiftAmt);
1027 bool isLshr = (Shr->getOpcode() == Instruction::LShr);
1028 BitMask1 = isLshr ? (BitMask1.lshr(ShrAmt) << ShlAmt)
    [all...]
InstCombineMulDivRem.cpp 80 if (I->getOpcode() == Instruction::LShr && !I->isExact()) {
353 // (lshr X, 31) * Y --> (ashr X, 31) & Y
354 // Y * (lshr X, 31) --> (ashr X, 31) & Y
893 BinaryOperator *LShr = BinaryOperator::CreateLShr(Op0, C1);
895 LShr->setIsExact();
896 return LShr;
917 BinaryOperator *LShr = BinaryOperator::CreateLShr(Op0, N);
919 LShr->setIsExact();
920 return LShr;
1017 // (X lshr C1) udiv C2 --> X udiv (C2 << C1
    [all...]
InstCombineNegator.cpp 189 case Instruction::LShr: {
  /src/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/
HexagonLoopIdiomRecognition.cpp 1006 case Instruction::LShr: // Shift right is ok.
1258 case Instruction::LShr:
1293 case Instruction::LShr:
1307 if (Opc == Instruction::Shl || Opc == Instruction::LShr)
1417 // Match lshr x, 1.
1479 // S = lshr S, IterCount
1481 // S = lshr PN, IterCount
1590 case Instruction::LShr:
1691 // (or (lshr x 1) 0x800.0) -> (xor (lshr x 1) 0x800.0
    [all...]
  /src/external/apache2/llvm/dist/llvm/include/llvm/Transforms/InstCombine/
InstCombiner.h 330 case Instruction::LShr: // 0 >>u X = 0
  /src/external/apache2/llvm/dist/llvm/lib/Transforms/AggressiveInstCombine/
AggressiveInstCombine.cpp 184 // %shr = lshr i32 %ShVal1, %sub
260 /// and (or (lshr X, C), ...), 1 --> (X & CMask) != 0
261 /// and (and (lshr X, C), ...), 1 --> (X & CMask) == CMask
310 if (I.getOpcode() != Instruction::LShr)
  /src/external/apache2/llvm/dist/llvm/lib/MC/
MCExpr.cpp 146 case MCBinaryExpr::LShr: OS << ">>"; break;
970 case MCBinaryExpr::LShr: Result = uint64_t(LHS) >> uint64_t(RHS); break;
  /src/external/apache2/llvm/dist/llvm/lib/Target/SystemZ/
SystemZTargetTransformInfo.cpp 159 case Instruction::LShr:
491 if (Opcode == Instruction::Shl || Opcode == Instruction::LShr ||
  /src/external/apache2/llvm/dist/llvm/lib/Target/Mips/
MipsFastISel.cpp 1975 // If AShr or LShr, then we need to make sure the operand0 is sign extended.
1976 if (Opcode == Instruction::AShr || Opcode == Instruction::LShr) {
1982 bool IsZExt = Opcode == Instruction::LShr;
2001 case Instruction::LShr:
2024 case Instruction::LShr:
2059 case Instruction::LShr:
  /src/external/apache2/llvm/dist/llvm/lib/Analysis/
CFLGraph.h 584 case Instruction::LShr:
DemandedBits.cpp 167 AB = AOut.lshr(ShiftAmt);
211 AB = AOut.lshr(ShiftAmt);
223 case Instruction::LShr:
ObjCARCInstKind.cpp 265 case Instruction::LShr:
  /src/external/apache2/llvm/dist/llvm/lib/Transforms/Utils/
LoopRotationUtils.cpp 727 case Instruction::LShr:

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