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    Searched refs:LWE (Results 1 - 3 of 3) sorted by relevancy

  /src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/
AMDGPUInstructionSelector.cpp 1451 static bool parseTexFail(uint64_t TexFailCtrl, bool &TFE, bool &LWE,
1458 LWE = (TexFailCtrl & 0x2) ? 1 : 0;
1494 bool LWE;
1497 TFE, LWE, IsTexFail))
1689 MIB.addImm(LWE); // lwe
1696 // An image load instruction with TFE/LWE only conditionally writes to its
1713 // With enable-prt-strict-null disabled, only initialize the extra TFE/LWE
SIISelLowering.cpp 5912 SDValue *LWE, bool &IsTexFail) {
5923 *LWE = DAG.getTargetConstant((Value & 0x2) ? 1 : 0, DL, MVT::i32);
6179 SDValue LWE;
6182 if (!parseTexFail(TexFail, DAG, &TFE, &LWE, IsTexFail))
6253 Ops.push_back(LWE); // lwe
10951 case AMDGPU::sub4: return 4; // Possible with TFE/LWE
10971 unsigned LWEIdx = AMDGPU::getNamedOperandIdx(Opcode, AMDGPU::OpName::lwe) - 1;
10983 // Work out which is the TFE/LWE lane if that is enabled.
11009 // Check if the use is for the TFE/LWE generated result at VGPRn+1
    [all...]
SIInstrInfo.cpp 3930 // being used TFE/LWE require an extra result register.
3937 const MachineOperand *LWE = getNamedOperand(MI, AMDGPU::OpName::lwe);
3944 // Adjust if using LWE or TFE
3945 if ((LWE && LWE->getImm()) || (TFE && TFE->getImm()))

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