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    Searched refs:LZ (Results 1 - 18 of 18) sorted by relevancy

  /src/external/gpl3/gcc/dist/libgcc/config/cris/
arit.c 38 #define LZ(v) __builtin_clz (v)
84 #ifdef LZ
87 quot_digits = LZ (b) - LZ (a);
176 #ifdef LZ
177 tmp = LZ (b);
255 #ifdef LZ
256 tmp = LZ (b);
  /src/external/gpl3/gcc.old/dist/libgcc/config/cris/
arit.c 38 #define LZ(v) __builtin_clz (v)
84 #ifdef LZ
87 quot_digits = LZ (b) - LZ (a);
176 #ifdef LZ
177 tmp = LZ (b);
255 #ifdef LZ
256 tmp = LZ (b);
  /src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/
AArch64ExpandImm.cpp 272 unsigned LZ = countLeadingZeros(Imm);
275 LastShift = ((63 - LZ) / 16) * 16;
AArch64ISelLowering.cpp 11859 unsigned LZ = countLeadingZeros((uint64_t)Val);
11860 unsigned Shift = (63 - LZ) / 16;
  /src/external/apache2/llvm/dist/llvm/lib/Target/PowerPC/
PPCISelDAGToDAG.cpp 921 unsigned LZ = countLeadingZeros<uint64_t>(Imm);
943 if (TZ > 15 && (LZ > 32 || LO > 32))
949 assert(LZ < 64 && "Unexpected leading zeros here.");
951 unsigned FO = countLeadingOnes<uint64_t>(Imm << LZ);
967 if ((LZ + FO + TZ) > 48) {
971 getI32Imm(TZ), getI32Imm(LZ));
974 // Shift right the Imm by (48 - LZ) bits to construct a negtive 16 bits value,
978 // +--LZ--||-15-bit-||--TO--+ +-------------|--16-bit--+
982 // Imm (Imm >> (48 - LZ) & 0xffff)
987 // LI8: sext many leading zeros RLDICL: rotate left (48 - LZ), clear left L
    [all...]
  /src/external/apache2/llvm/dist/llvm/include/llvm/DebugInfo/PDB/
PDBTypes.h 163 LZ,
  /src/external/apache2/llvm/dist/llvm/lib/DebugInfo/PDB/
PDBExtras.cpp 342 CASE_OUTPUT_ENUM_CLASS_NAME(PDB_SourceCompression, LZ, OS)
  /src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/Utils/
AMDGPUBaseInfo.h 321 MIMGBaseOpcode LZ;
  /src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/
AMDGPUISelLowering.cpp 2404 // uint lz = clz(u);
2405 // uint e = (u != 0) ? 127U + 63U - lz : 0;
2406 // u = (u << lz) & 0x7fffffffffffffffUL;
2439 SDValue LZ = DAG.getNode(ISD::CTLZ_ZERO_UNDEF, SL, MVT::i64, L);
2440 LZ = DAG.getNode(ISD::TRUNCATE, SL, MVT::i32, LZ);
2445 DAG.getNode(ISD::SUB, SL, MVT::i32, K, LZ),
2449 DAG.getNode(ISD::SHL, SL, MVT::i64, L, LZ),
3084 unsigned LZ = Known.countMinLeadingZeros();
3085 if (LZ < RHSVal
    [all...]
AMDGPUInstructionSelector.cpp 1565 IntrOpcode = LZMappingInfo->LZ; // set new opcode to _lz variant of _l
AMDGPULegalizerInfo.cpp 4203 AMDGPU::getImageDimInstrinsicByBaseOpcode(LZMappingInfo->LZ,
SIISelLowering.cpp 6063 IntrOpcode = LZMappingInfo->LZ; // set new opcode to _lz variant of _l
  /src/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/
HexagonISelDAGToDAG.cpp 1135 uint32_t LZ = countLeadingZeros(Mask);
1137 if (TZ + M1 + LZ != 32)
1143 if (LZ > CV)
  /src/external/apache2/llvm/dist/llvm/lib/Analysis/
ScalarEvolution.cpp 3147 unsigned LZ = RHSC->getAPInt().countLeadingZeros();
3148 unsigned MaxShiftAmt = getTypeSizeInBits(Ty) - LZ - 1;
6618 unsigned LZ = A.countLeadingZeros();
6626 APInt::getLowBitsSet(BitWidth, BitWidth - LZ - TZ).shl(TZ);
6627 if ((LZ != 0 || TZ != 0) && !((~A & ~Known.Zero) & EffectiveMask)) {
6649 IntegerType::get(getContext(), BitWidth - LZ - TZ)),
  /src/external/apache2/llvm/dist/llvm/lib/CodeGen/GlobalISel/
LegalizerHelper.cpp 5605 // uint lz = clz(u);
5606 // uint e = (u != 0) ? 127U + 63U - lz : 0;
5607 // u = (u << lz) & 0x7fffffffffffffffUL;
5617 auto LZ = MIRBuilder.buildCTLZ_ZERO_UNDEF(S32, Src);
5620 auto Sub = MIRBuilder.buildSub(S32, K, LZ);
5626 auto ShlLZ = MIRBuilder.buildShl(S64, Src, LZ);
  /src/crypto/external/apache2/openssl/dist/test/recipes/30-test_evp_data/
evppkey_ecdh.txt 1770 0P7kxX+1U2LNWxaORO+LZ+zvvaVn0x42npCcYxnmfmy5sexrRA4kvUumZdcrRQhY
  /src/crypto/external/bsd/openssl/dist/test/recipes/30-test_evp_data/
evppkey_ecdh.txt 1770 0P7kxX+1U2LNWxaORO+LZ+zvvaVn0x42npCcYxnmfmy5sexrRA4kvUumZdcrRQhY
  /src/crypto/external/bsd/openssl.old/dist/test/recipes/30-test_evp_data/
evppkey.txt 4120 0P7kxX+1U2LNWxaORO+LZ+zvvaVn0x42npCcYxnmfmy5sexrRA4kvUumZdcrRQhY

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