| /src/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/ |
| RegisterPressure.h | 41 LaneBitmask LaneMask;
43 RegisterMaskPair(Register RegUnit, LaneBitmask LaneMask)
44 : RegUnit(RegUnit), LaneMask(LaneMask) {}
264 LaneBitmask LaneMask;
266 IndexMaskPair(unsigned Index, LaneBitmask LaneMask)
267 : Index(Index), LaneMask(LaneMask) {}
300 return I->LaneMask;
303 /// Mark the \p Pair.LaneMask lanes of \p Pair.Reg as live
[all...] |
| LiveIntervalCalc.h | 33 /// of the live interval @p LI, corresponding to lane mask @p LaneMask,
37 /// If @p LR is a main range, the @p LaneMask should be set to ~0, i.e.
39 void extendToUses(LiveRange &LR, Register Reg, LaneBitmask LaneMask,
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| ScheduleDAGInstrs.h | 54 LaneBitmask LaneMask;
57 VReg2SUnit(unsigned VReg, LaneBitmask LaneMask, SUnit *SU)
58 : VirtReg(VReg), LaneMask(LaneMask), SU(SU) {}
69 VReg2SUnitOperIdx(unsigned VReg, LaneBitmask LaneMask,
71 : VReg2SUnit(VReg, LaneMask, SU), OperandIndex(OperandIndex) {}
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| LiveInterval.h | 684 /// A live range for subregisters. The LaneMask specifies which parts of the
690 LaneBitmask LaneMask;
693 SubRange(LaneBitmask LaneMask) : LaneMask(LaneMask) {}
696 SubRange(LaneBitmask LaneMask, const LiveRange &Other,
698 : LiveRange(Other, Allocator), LaneMask(LaneMask) {}
780 LaneBitmask LaneMask) {
781 SubRange *Range = new (Allocator) SubRange(LaneMask);
[all...] |
| TargetRegisterInfo.h | 56 const LaneBitmask LaneMask;
205 return LaneMask;
380 /// Try to find one or more subregister indexes to cover \p LaneMask.
386 LaneBitmask LaneMask,
635 /// Transforms a LaneMask computed for one subregister to the lanemask that
645 /// Transform a lanemask given for a virtual register to the corresponding
646 /// lanemask before using subregister with index \p IdxA.
653 LaneBitmask LaneMask) const {
655 return LaneMask;
[all...] |
| MachineBasicBlock.h | 104 LaneBitmask LaneMask;
106 RegisterMaskPair(MCPhysReg PhysReg, LaneBitmask LaneMask)
107 : PhysReg(PhysReg), LaneMask(LaneMask) {}
368 LaneBitmask LaneMask = LaneBitmask::getAll()) {
369 LiveIns.push_back(RegisterMaskPair(PhysReg, LaneMask));
390 LaneBitmask LaneMask = LaneBitmask::getAll());
394 LaneBitmask LaneMask = LaneBitmask::getAll()) const;
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| RegisterScavenging.h | 177 void setRegUsed(Register Reg, LaneBitmask LaneMask = LaneBitmask::getAll());
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| /src/external/apache2/llvm/dist/llvm/include/llvm/MC/ |
| LaneBitmask.h | 93 inline Printable PrintLaneMask(LaneBitmask LaneMask) {
94 return Printable([LaneMask](raw_ostream &OS) {
95 OS << format(LaneBitmask::FormatStr, LaneMask.getAsInteger());
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| /src/external/apache2/llvm/dist/llvm/lib/CodeGen/ |
| RegisterPressure.cpp | 101 if (!P.LaneMask.all())
102 dbgs() << ':' << PrintLaneMask(P.LaneMask);
109 if (!P.LaneMask.all())
110 dbgs() << ':' << PrintLaneMask(P.LaneMask);
367 LaneBitmask::getNone(), Pair.LaneMask);
378 return I->LaneMask;
384 assert(Pair.LaneMask.any());
391 I->LaneMask |= Pair.LaneMask;
403 I->LaneMask = LaneBitmask::getNone()
[all...] |
| ScheduleDAGInstrs.cpp | 386 return (RegUse->LaneMask & getLaneMaskForMO(MO)).none();
436 LaneBitmask LaneMask = I->LaneMask;
438 if ((LaneMask & KillLaneMask).none()) {
443 if ((LaneMask & DefLaneMask).any()) {
453 LaneMask &= ~KillLaneMask;
455 if (LaneMask.any()) {
456 I->LaneMask = LaneMask;
474 LaneBitmask LaneMask = DefLaneMask
[all...] |
| MachineVerifier.cpp | 230 LaneBitmask LaneMask) const;
236 void report_context_lanemask(LaneBitmask LaneMask) const;
246 LaneBitmask LaneMask = LaneBitmask::getNone());
250 LaneBitmask LaneMask = LaneBitmask::getNone());
266 LaneBitmask LaneMask = LaneBitmask::getNone());
517 LaneBitmask LaneMask) const {
520 if (LaneMask.any())
521 report_context_lanemask(LaneMask);
552 void MachineVerifier::report_context_lanemask(LaneBitmask LaneMask) const {
553 errs() << "- lanemask: " << PrintLaneMask(LaneMask) << '\n'
[all...] |
| RenameIndependentSubregs.cpp | 183 LaneBitmask LaneMask = TRI.getSubRegIndexLaneMask(SubRegIdx);
187 if ((SR.LaneMask & LaneMask).none())
227 LaneBitmask LaneMask = TRI.getSubRegIndexLaneMask(SubRegIdx);
232 if ((SR.LaneMask & LaneMask).none())
285 SubRanges[ID-1] = Intervals[ID]->createSubRange(Allocator, SR.LaneMask);
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| LiveIntervals.cpp | 377 Register Reg, LaneBitmask LaneMask) {
388 if ((SR.LaneMask & M).any()) {
389 assert(SR.LaneMask == M && "Expecting lane masks to match exactly");
397 const LiveRange &OldRange = getSubRange(LI, LaneMask);
444 assert(LaneMask.any() &&
447 LI.computeSubRangeUndefs(Undefs, LaneMask, *MRI, *Indexes);
579 LaneBitmask LaneMask = TRI->getSubRegIndexLaneMask(SubReg);
580 if ((LaneMask & SR.LaneMask).none())
608 extendSegmentsToUses(NewLR, WorkList, Reg, SR.LaneMask);
[all...] |
| LiveInterval.cpp | 881 /// of the mask describe by \p LaneMask and if not, remove that value
884 LaneBitmask LaneMask,
914 if ((ExpectedDefMask & LaneMask).none())
931 BumpPtrAllocator &Allocator, LaneBitmask LaneMask,
935 LaneBitmask ToApply = LaneMask;
937 LaneBitmask SRMask = SR.LaneMask;
938 LaneBitmask Matching = SRMask & LaneMask;
944 // The subrange fits (it does not cover bits outside \p LaneMask).
948 // Reduce lanemask of existing lane to non-matching part.
949 SR.LaneMask = SRMask & ~Matching
[all...] |
| RegisterCoalescer.cpp | 148 /// A LaneMask to remember on which subregister live ranges we need to call
251 /// LaneMask are split as necessary. @p LaneMask are the lanes that
255 LaneBitmask LaneMask, CoalescerPair &CP,
261 LaneBitmask LaneMask, const CoalescerPair &CP);
988 MaskA |= SA.LaneMask;
991 Allocator, SA.LaneMask,
1008 if ((SB.LaneMask & MaskA).any())
1231 IntB.computeSubRangeUndefs(Undefs, SR.LaneMask, *MRI,
1409 // Remap subranges to new lanemask and change register class
[all...] |
| RDFRegisters.cpp | 37 if (RC->LaneMask != RI.RegClass->LaneMask) {
67 UI.Mask = RC->LaneMask;
177 if (RC != nullptr && (RR.Mask & RC->LaneMask) == RC->LaneMask)
237 LaneBitmask RCM = RI.RegClass ? RI.RegClass->LaneMask
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| VirtRegMap.cpp | 304 LaneBitmask LaneMask;
313 LaneMask |= SR->LaneMask;
315 if (LaneMask.none())
318 MBB->addLiveIn(PhysReg, LaneMask);
385 if ((SR.LaneMask & UseMask).any() && SR.liveAt(BaseIndex))
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| LiveRangeEdit.cpp | 49 LI.createSubRange(Alloc, S.LaneMask);
252 LaneBitmask LaneMask = TRI.getSubRegIndexLaneMask(SubReg);
254 if ((S.LaneMask & LaneMask).any() && S.Query(Idx).isKill())
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| SplitKit.cpp | 412 if (S.LaneMask == LM)
420 if ((S.LaneMask & LM) == LM)
437 auto &PS = getSubRangeForMask(S.LaneMask, Edit->getParent());
461 if ((S.LaneMask & LM).any())
539 LaneBitmask LaneMask = TRI.getSubRegIndexLaneMask(SubIdx);
540 DestLI.refineSubRanges(Allocator, LaneMask,
549 LaneBitmask LaneMask, MachineBasicBlock &MBB,
552 if (LaneMask.all() || LaneMask == MRI.getMaxLaneMaskForVReg(FromReg)) {
566 // exists find the one covering the most lanemask bits
[all...] |
| MachineBasicBlock.cpp | 419 if (!LI.LaneMask.all())
420 OS << ":0x" << PrintLaneMask(LI.LaneMask);
557 void MachineBasicBlock::removeLiveIn(MCPhysReg Reg, LaneBitmask LaneMask) {
563 I->LaneMask &= ~LaneMask;
564 if (I->LaneMask.none())
575 bool MachineBasicBlock::isLiveIn(MCPhysReg Reg, LaneBitmask LaneMask) const {
578 return I != livein_end() && (I->LaneMask & LaneMask).any();
592 LaneBitmask LaneMask = I->LaneMask
[all...] |
| LiveRegUnits.cpp | 77 LiveUnits.addRegMasked(LI.PhysReg, LI.LaneMask);
|
| TargetRegisterInfo.cpp | 525 LaneBitmask LaneMask, SmallVectorImpl<unsigned> &NeededIndexes) const {
536 if (SubRegMask == LaneMask) {
541 // The index must not cover any lanes outside \p LaneMask.
542 if ((SubRegMask & ~LaneMask).any())
561 LaneBitmask LanesLeft = LaneMask & ~getSubRegIndexLaneMask(BestIdx);
|
| /src/external/apache2/llvm/dist/llvm/utils/TableGen/ |
| CodeGenRegisters.cpp | 107 if (LaneMask.any())
108 return LaneMask;
111 LaneMask = LaneBitmask::getAll();
118 LaneMask = M;
119 return LaneMask;
1443 Twine("Ran out of lanemask bits to represent subregister ")
1446 Idx.LaneMask = LaneBitmask::getLane(Bit);
1449 Idx.LaneMask = LaneBitmask::getNone();
1468 unsigned DstBit = Idx.LaneMask.getHighestLane();
1469 assert(Idx.LaneMask == LaneBitmask::getLane(DstBit) &
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/ |
| RDFCopy.cpp | 124 if ((RC.LaneMask & RR.Mask) == RC.LaneMask)
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/ |
| GCNRegPressure.cpp | 234 I->LaneMask |= UsedMask;
253 LiveMask |= S.LaneMask;
313 AtMIPressure.inc(U.RegUnit, LiveMask, LiveMask | U.LaneMask, *MRI);
336 LiveMask |= U.LaneMask;
372 It.second &= ~S.LaneMask;
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