| /src/external/apache2/llvm/dist/llvm/tools/llvm-mca/Views/ |
| InstructionInfoView.cpp | 33 TempStream << "[1]: #uOps\n[2]: Latency\n[3]: RThroughput\n"
51 TempStream << IIVDEntry.Latency << " ";
52 if (IIVDEntry.Latency < 10)
54 else if (IIVDEntry.Latency < 100)
112 IIVDEntry.Latency = MCSchedModel::computeInstrLatency(STI, SCDesc);
113 // Add extra latency due to delays in the forwarding data paths.
114 IIVDEntry.Latency += MCSchedModel::getForwardingDelayCycles(
127 {"Latency", IIVD.Latency},
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| InstructionInfoView.h | 12 /// The goal fo the instruction info view is to print the latency and reciprocal
21 /// [2]: Latency
60 unsigned Latency = 0;
|
| /src/external/apache2/llvm/dist/llvm/include/llvm/MC/ |
| MCInstrItineraries.h | 146 /// Return the total stage latency of the given class. The latency is
156 unsigned Latency = 0, StartCycle = 0;
159 Latency = std::max(Latency, StartCycle + IS->getCycles());
162 return Latency;
202 /// Compute and return the use operand latency of a given itinerary
|
| /src/external/apache2/llvm/dist/llvm/lib/MC/MCDisassembler/ |
| Disassembler.cpp | 166 /// Gets latency information for \p Inst from the itinerary
168 /// \return The maximum expected latency over all the operands or -1
184 int Latency = 0;
187 Latency = std::max(Latency, IID.getOperandCycle(SCClass, OpIdx));
189 return Latency;
192 /// Gets latency information for \p Inst, based on \p DC information.
193 /// \return The maximum expected latency over all the definitions or -1
216 // Compute output latency.
217 int16_t Latency = 0
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/MC/ |
| MCSchedule.cpp | 42 int Latency = 0;
45 // Lookup the definition's write latency in SubtargetInfo.
48 // Early exit if we found an invalid latency.
51 Latency = std::max(Latency, static_cast<int>(WLEntry->Cycles));
53 return Latency;
|
| /src/external/apache2/llvm/dist/llvm/tools/llvm-xray/ |
| xray-account.h | 63 void recordLatency(int32_t FuncId, uint64_t Latency) {
64 FunctionLatencies[FuncId].push_back(Latency);
|
| /src/external/apache2/llvm/dist/llvm/lib/MCA/ |
| InstrBuilder.cpp | 155 // On top of those 2cy, SchedWriteRes explicitly specifies an extra latency
156 // of 3 cycles for HWPort01. This tool assumes that the 3cy latency is an
157 // extra delay on top of the 2 cycles latency.
211 // Artificially set an arbitrarily high latency (100cy).
216 int Latency = MCSchedModel::computeInstrLatency(STI, SCDesc);
217 // If latency is unknown, then conservatively assume a MaxLatency of 100cy.
218 ID.MaxLatency = Latency < 0 ? 100U : static_cast<unsigned>(Latency);
330 Write.Latency =
334 // Assign a default latency for this write
[all...] |
| /src/external/apache2/llvm/dist/llvm/tools/llvm-exegesis/lib/ |
| Target.cpp | 61 case InstructionBenchmark::Latency:
78 case InstructionBenchmark::Latency:
81 const char *ModeName = Mode == InstructionBenchmark::Latency
82 ? "latency"
|
| LatencyBenchmarkRunner.cpp | 25 assert((Mode == InstructionBenchmark::Latency ||
96 case InstructionBenchmark::Latency:
97 ModeName = "latency";
|
| BenchmarkResult.h | 62 enum ModeE { Unknown, Latency, Uops, InverseThroughput };
|
| SchedClassResolution.cpp | 267 if (Mode == InstructionBenchmark::Latency) {
268 assert(NumMeasurements == 1 && "Latency is a single measure.");
271 // Find the latency.
|
| /src/external/apache2/llvm/dist/llvm/lib/CodeGen/SelectionDAG/ |
| ScheduleDAGSDNodes.cpp | 41 // This allows the latency-based scheduler to notice high latency instructions
43 // balancing scheduler heuristics than with the actual machine latency.
45 "sched-high-latency-cycles", cl::Hidden, cl::init(10),
46 cl::desc("Roughly estimate the number of cycles that 'long latency'"
93 SU->Latency = Old->Latency;
404 // Schedule zero-latency TokenFactor below any nodes that may increase the
420 // Assign the Latency field of NodeSUnit using target-provided information.
501 // If this is a ctrl dep, latency is 1
[all...] |
| ScheduleDAGVLIW.cpp | 58 /// been issued, but their results are not ready yet (due to the latency of
196 assert(PendingQueue[i]->getDepth() > CurCycle && "Negative latency?");
241 if (FoundSUnit->Latency) // Don't increment CurCycle for pseudo-ops!
|
| /src/external/apache2/llvm/dist/llvm/lib/CodeGen/ |
| TargetSchedule.cpp | 34 cl::desc("Use TargetSchedModel for latency lookup"));
37 cl::desc("Use InstrItineraryData for latency lookup"));
122 // The machine model may explicitly specify an invalid latency, which
123 // effectively means infinite latency. Since users of the TargetSchedule API
124 // don't know how to handle this, we convert it to a very large latency that is
204 // No operand latency was found.
207 // Expected latency is the max of the stage latency and itinerary props.
208 // Rather than directly querying InstrItins stage latency, we call a TII
209 // hook to allow subtargets to specialize latency. This hook is onl
[all...] |
| CriticalAntiDepBreaker.cpp | 149 // In the case of a latency tie, prefer an anti-dependency edge over
461 if (!Max || SU->getDepth() + SU->Latency > Max->getDepth() + Max->Latency)
468 LLVM_DEBUG(dbgs() << "Critical path has total latency "
469 << (Max->getDepth() + Max->Latency) << "\n");
|
| ScheduleDAGInstrs.cpp | 240 // Only use any non-zero latency for real defs/uses, in contrast to
252 // Adjust the dependence latency using operand def/use information,
302 // dependencies we use a latency of 0 because for a multi-issue
305 // TODO: Using a latency of 1 here for output dependencies assumes
473 // is also useful if output latency exceeds def-use latency.
549 unsigned Latency) {
552 Dep.setLatency(Latency);
584 // Assign the Latency field of SU using target-provided information.
585 SU->Latency = SchedModel.computeInstrLatency(SU->getInstr())
[all...] |
| /src/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/ |
| ScheduleDAG.h | 94 /// Latency field of the predecessor, however advanced models may provide
96 unsigned Latency;
114 Latency = 0;
118 Latency = 1;
124 : Dep(S, Order), Contents(), Latency(0) {
128 /// Returns true if the specified SDep is equivalent except for latency.
132 return overlaps(Other) && Latency == Other.Latency;
139 /// Returns the latency value for this edge, which roughly means the
143 return Latency;
[all...] |
| ScheduleDAGInstrs.h | 207 unsigned Latency = 0);
210 void addChainDependencies(SUnit *SU, SUList &SUs, unsigned Latency) {
212 addChainDependency(SU, Entry, Latency);
325 /// important when the definition latency of the return value(s) are too
|
| MachinePipeliner.h | 223 /// given node in which each edge has latency 0
232 /// arbitrary node in which each edge has latency 0
319 unsigned Latency = 0;
326 Latency = 0;
341 Latency += SUnitLatency.second;
383 unsigned getLatency() { return Latency; }
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/ |
| GCNILPSched.cpp | 131 // Return 0 if latency-based priority is equivalent.
134 // been scheduled will induce a copy. Model this as an extra cycle of latency.
138 // If either node is scheduling for latency, sort them by height/depth
139 // and latency.
151 LLVM_DEBUG(dbgs() << " Comparing latency of SU (" << left->NodeNum
156 if (left->Latency != right->Latency)
157 return left->Latency > right->Latency ? 1 : -1;
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/ |
| HexagonSubtarget.cpp | 45 static cl::opt<bool> EnableTCLatencySched("enable-tc-latency-sched",
213 // Update the latency of chain edges between v60 vector load or store
371 // latency.
387 /// Perform target specific adjustments to the latency of a schedule
399 // Instructions with .new operands have zero latency.
411 // Set the latency for a copy to zero since we hope that is will get removed.
416 // the correct latency.
516 int Latency = (InstrInfo.getOperandLatency(&InstrItins, *SrcI,
519 // For some instructions (ex: COPY), we might end up with < 0 latency
521 Latency = std::max(Latency, 0)
[all...] |
| /src/external/apache2/llvm/dist/llvm/include/llvm/MCA/ |
| Instruction.h | 42 // Write latency. Number of cycles before write-back stage.
43 unsigned Latency;
101 // On instruction issue, this field is set equal to the write latency.
164 unsigned getLatency() const { return WD->Latency; }
173 // number of cycles to subtract from the latency of this data dependency.
223 /// Tracks register operand latency in cycles.
238 // the latency of all the dependent writes. It defaults to UNKNOWN_CYCLES.
384 // A zero latency instruction doesn't consume any scheduler resources.
450 IS_PENDING, // Instruction is not ready, but operand latency is known.
460 // This value defaults to the instruction latency. This instruction i
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/X86/ |
| X86CmovConversion.cpp | 193 // memory latency by blocking speculative execution.
408 // instruction latency + max operand depth.
410 // CMOV latency + getDepthOfOptCmov(True-Op-Depth, False-Op-depth)
411 // TODO: Find a better way to estimate the latency of the branch instruction
412 // rather than using the CMOV latency.
465 unsigned Latency = TSchedModel.computeInstrLatency(&MI);
466 DepthMap[&MI] = {MIDepth += Latency, MIDepthOpt += Latency};
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/ARM/ |
| ARMBaseInstrInfo.cpp | 3898 // Result latency is issue cycle + 2: E2.
3906 // Result latency is AGU cycles + 2.
3998 // latency might be determinable dynamically. Let the target try to
4039 // We can't seem to determine the result latency of the def, assume it's 2.
4151 /// adjusted latency is at least one cycle.
4182 // FIXME: Properly handle all of the latency adjustments for address
4335 // No operand latency. The caller may fall back to getInstrLatency.
4381 // Otherwise it takes the instruction latency (generally one).
4382 unsigned Latency = getInstrLatency(ItinData, DefMI);
4388 if (Latency > 0 && Subtarget.isThumb2())
[all...] |
| /src/sys/external/bsd/acpica/dist/common/ |
| dmtbinfo2.c | 637 {ACPI_DMT_UINT32, ACPI_LPIT0_OFFSET (Latency), "Latency", 0},
1409 {ACPI_DMT_UINT64, ACPI_MPST2_OFFSET (ExitLatency), "Exit Latency", 0},
1678 {ACPI_DMT_UINT32, ACPI_PCCT0_OFFSET (Latency), "Command Latency", 0},
1698 {ACPI_DMT_UINT32, ACPI_PCCT1_OFFSET (Latency), "Command Latency", 0},
1718 {ACPI_DMT_UINT32, ACPI_PCCT2_OFFSET (Latency), "Command Latency", 0},
1741 {ACPI_DMT_UINT32, ACPI_PCCT3_OFFSET (Latency), "Command Latency", 0}
[all...] |
