| /src/external/bsd/openldap/dist/libraries/liblunicode/ucdata/ |
| MUTTUCData.txt | 212 E900;DEVANAGARI KSHA LIGATURE;Lo;0;L;0915 094D 0937;;;;N;;;;;
213 E901;DEVANAGARI GNYA LIGATURE;Lo;0;L;091C 094D 091E;;;;N;;;;;
214 E902;DEVANAGARI TTA LIGATURE;Lo;0;L;0924 094D 0924;;;;N;;;;;
215 E903;DEVANAGARI TRA LIGATURE;Lo;0;L;0924 094D 0930;;;;N;;;;;
216 E904;DEVANAGARI SHCHA LIGATURE;Lo;0;L;0936 094D 091B;;;;N;;;;;
217 E905;DEVANAGARI SHRA LIGATURE;Lo;0;L;0936 094D 0930;;;;N;;;;;
218 E906;DEVANAGARI SHVA LIGATURE;Lo;0;L;0936 094D 0935;;;;N;;;;;
219 E907;DEVANAGARI KRA LIGATURE;Lo;0;L;;;;;N;;;;;
220 E908;DEVANAGARI JRA LIGATURE;Lo;0;L;;;;;N;;;;;
221 E909;DEVANAGARI ZRA LIGATURE;Lo;0;L;;;;;N;;;;
[all...] |
| /src/sys/external/bsd/acpica/dist/utilities/ |
| utmath.c | 55 UINT32 Lo;
110 ACPI_MUL_64_BY_32 (0, MultiplicandOvl.Part.Lo, Multiplier,
111 Product.Part.Lo, Carry32);
154 OperandOvl.Part.Hi = OperandOvl.Part.Lo;
155 OperandOvl.Part.Lo = 0;
159 OperandOvl.Part.Lo, Count);
199 OperandOvl.Part.Lo = OperandOvl.Part.Hi;
204 OperandOvl.Part.Lo, Count);
368 ACPI_DIV_64_BY_32 (Remainder32, DividendOvl.Part.Lo, Divisor,
369 Quotient.Part.Lo, Remainder32)
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/CodeGen/SelectionDAG/ |
| LegalizeTypes.h | 229 SDValue JoinIntegers(SDValue Lo, SDValue Hi);
236 void SplitInteger(SDValue Op, SDValue &Lo, SDValue &Hi);
238 SDValue &Lo, SDValue &Hi);
406 /// equal to the bits of Lo; the high bits exactly equal Hi.
408 /// method returns the two i32's, with Lo being equal to the lower 32 bits of
410 void GetExpandedInteger(SDValue Op, SDValue &Lo, SDValue &Hi);
411 void SetExpandedInteger(SDValue Op, SDValue Lo, SDValue Hi);
415 void ExpandIntRes_ANY_EXTEND (SDNode *N, SDValue &Lo, SDValue &Hi);
416 void ExpandIntRes_AssertSext (SDNode *N, SDValue &Lo, SDValue &Hi);
417 void ExpandIntRes_AssertZext (SDNode *N, SDValue &Lo, SDValue &Hi)
[all...] |
| LegalizeTypesGeneric.cpp | 13 // computation in two identical registers of a smaller type. The Lo/Hi part
31 // These routines assume that the Lo/Hi part is stored first in memory on
32 // little/big-endian machines, followed by the Hi/Lo part. This means that
33 // they cannot be used as is on vectors, for which Lo is always stored first.
35 SDValue &Lo, SDValue &Hi) {
37 GetExpandedOp(Op, Lo, Hi);
40 void DAGTypeLegalizer::ExpandRes_BITCAST(SDNode *N, SDValue &Lo, SDValue &Hi) {
57 SplitInteger(GetSoftenedFloat(InOp), Lo, Hi);
58 Lo = DAG.getNode(ISD::BITCAST, dl, NOutVT, Lo);
[all...] |
| LegalizeTypes.cpp | 764 void DAGTypeLegalizer::GetExpandedInteger(SDValue Op, SDValue &Lo,
768 Lo = getSDValue(Entry.first);
772 void DAGTypeLegalizer::SetExpandedInteger(SDValue Op, SDValue Lo,
774 assert(Lo.getValueType() ==
776 Hi.getValueType() == Lo.getValueType() &&
778 // Lo/Hi may have been newly allocated, if so, add nodeid's as relevant.
779 AnalyzeNewValue(Lo);
786 DAG.transferDbgValues(Op, Lo, Hi.getValueSizeInBits(),
787 Lo.getValueSizeInBits());
789 DAG.transferDbgValues(Op, Lo, 0, Lo.getValueSizeInBits(), false)
[all...] |
| LegalizeIntegerTypes.cpp | 378 SDValue Lo, Hi;
379 GetSplitVector(N->getOperand(0), Lo, Hi);
380 Lo = BitConvertToInteger(Lo);
384 std::swap(Lo, Hi);
389 JoinIntegers(Lo, Hi));
1179 SDValue Lo = GetPromotedInteger(N->getOperand(1));
1184 EVT VT = Lo.getValueType();
1203 Lo = DAG.getZeroExtendInReg(Lo, DL, OldVT)
[all...] |
| LegalizeFloatTypes.cpp | 1159 SDValue Lo, Hi;
1160 Lo = Hi = SDValue();
1174 case ISD::UNDEF: SplitRes_UNDEF(N, Lo, Hi); break;
1175 case ISD::SELECT: SplitRes_SELECT(N, Lo, Hi); break;
1176 case ISD::SELECT_CC: SplitRes_SELECT_CC(N, Lo, Hi); break;
1178 case ISD::MERGE_VALUES: ExpandRes_MERGE_VALUES(N, ResNo, Lo, Hi); break;
1179 case ISD::BITCAST: ExpandRes_BITCAST(N, Lo, Hi); break;
1180 case ISD::BUILD_PAIR: ExpandRes_BUILD_PAIR(N, Lo, Hi); break;
1181 case ISD::EXTRACT_ELEMENT: ExpandRes_EXTRACT_ELEMENT(N, Lo, Hi); break;
1182 case ISD::EXTRACT_VECTOR_ELT: ExpandRes_EXTRACT_VECTOR_ELT(N, Lo, Hi); break
[all...] |
| LegalizeVectorTypes.cpp | 898 SDValue Lo, Hi;
914 case ISD::MERGE_VALUES: SplitRes_MERGE_VALUES(N, ResNo, Lo, Hi); break;
916 case ISD::SELECT: SplitRes_SELECT(N, Lo, Hi); break;
917 case ISD::SELECT_CC: SplitRes_SELECT_CC(N, Lo, Hi); break;
918 case ISD::UNDEF: SplitRes_UNDEF(N, Lo, Hi); break;
919 case ISD::BITCAST: SplitVecRes_BITCAST(N, Lo, Hi); break;
920 case ISD::BUILD_VECTOR: SplitVecRes_BUILD_VECTOR(N, Lo, Hi); break;
921 case ISD::CONCAT_VECTORS: SplitVecRes_CONCAT_VECTORS(N, Lo, Hi); break;
922 case ISD::EXTRACT_SUBVECTOR: SplitVecRes_EXTRACT_SUBVECTOR(N, Lo, Hi); break;
923 case ISD::INSERT_SUBVECTOR: SplitVecRes_INSERT_SUBVECTOR(N, Lo, Hi); break
[all...] |
| /src/external/apache2/llvm/dist/libcxx/include/__support/ibm/ |
| gettod_zos.h | 23 uint64_t Lo;
37 uint64_t ns = ((Value.Hi & 0x0F) << 8) + (Value.Lo >> 56);
|
| /src/external/apache2/llvm/dist/llvm/include/llvm/Support/ |
| SwapByteOrder.h | 60 uint16_t Lo = value >> 8;
61 return Hi | Lo;
88 uint32_t Lo = ByteSwap_32(uint32_t(value >> 32));
89 return (Hi << 32) | Lo;
|
| /src/external/apache2/llvm/dist/llvm/lib/CodeGen/AsmPrinter/ |
| AsmPrinterDwarf.cpp | 55 /// Emit something like ".uleb128 Hi-Lo".
57 const MCSymbol *Lo) const {
58 OutStreamer->emitAbsoluteSymbolDiffAsULEB128(Hi, Lo);
211 void AsmPrinter::emitCallSiteOffset(const MCSymbol *Hi, const MCSymbol *Lo,
215 emitLabelDifferenceAsULEB128(Hi, Lo);
217 emitLabelDifference(Hi, Lo, GetSizeOfEncodedValue(Encoding));
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/Mips/ |
| Mips16ISelDAGToDAG.cpp | 47 SDNode *Lo = nullptr, *Hi = nullptr;
54 Lo = CurDAG->getMachineNode(Opcode, DL, Ty, MVT::Glue, InFlag);
55 InFlag = SDValue(Lo, 1);
61 return std::make_pair(Lo, Hi);
146 // addiu $2, $2, %lo($CPI1_0)
150 // lwc1 $f0, %lo($CPI1_0)($2)
151 if (Addr.getOperand(1).getOpcode() == MipsISD::Lo ||
|
| MipsISelLowering.h | 78 // No relation with Mips Lo register
79 Lo,
376 // (add (load (wrapper $gp, %got(sym)), %lo(sym))
387 SDValue Lo = DAG.getNode(MipsISD::Lo, DL, Ty,
389 return DAG.getNode(ISD::ADD, DL, Ty, Load, Lo);
408 // (load (wrapper (add %hi(sym), $gp), %lo(sym)))
425 // (add %hi(sym), %lo(sym))
432 SDValue Lo = getTargetNode(N, Ty, DAG, MipsII::MO_ABS_LO);
435 DAG.getNode(MipsISD::Lo, DL, Ty, Lo))
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/BPF/Disassembler/ |
| BPFDisassembler.cpp | 143 uint64_t Lo, Hi;
153 Lo = (Bytes[4] << 0) | (Bytes[5] << 8) | (Bytes[6] << 16) | (Bytes[7] << 24);
157 Lo = (Bytes[4] << 24) | (Bytes[5] << 16) | (Bytes[6] << 8) | (Bytes[7] << 0);
159 Insn = Make_64(Hi, Lo);
|
| /src/external/apache2/llvm/dist/llvm/lib/IR/ |
| MDBuilder.cpp | 84 MDNode *MDBuilder::createRange(const APInt &Lo, const APInt &Hi) {
85 assert(Lo.getBitWidth() == Hi.getBitWidth() && "Mismatched bitwidths!");
87 Type *Ty = IntegerType::get(Context, Lo.getBitWidth());
88 return createRange(ConstantInt::get(Ty, Lo), ConstantInt::get(Ty, Hi));
91 MDNode *MDBuilder::createRange(Constant *Lo, Constant *Hi) {
93 if (Hi == Lo)
96 // Return the range [Lo, Hi).
97 return MDNode::get(Context, {createConstant(Lo), createConstant(Hi)});
|
| /src/lib/libm/arch/vax/ |
| n_atan2.S | 136 movq $0x21b1879a3bc2a2fc,%r8 # Lo=-.17092002525602665777d-17
150 clrq %r6 # Hi=%r6=0, Lo=%r8=0
155 movq $0xf0ea17b2bf912295,%r8 # Lo=.10147340032515978826d-17
165 movq $0x06e0145c26332326,%r8 # Lo=.22517417741562176079d-17
173 movq $0x06e0145c263322a6,%r8 # Lo=.11258708870781088040d-17
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/Lanai/ |
| LanaiISelLowering.cpp | 1116 case LanaiISD::LO:
1117 return "LanaiISD::LO";
1149 SDValue Lo = DAG.getTargetConstantPool(C, MVT::i32, N->getAlign(),
1152 Lo = DAG.getNode(LanaiISD::LO, DL, MVT::i32, Lo);
1153 SDValue Result = DAG.getNode(ISD::OR, DL, MVT::i32, Hi, Lo);
1184 SDValue Lo = DAG.getTargetGlobalAddress(
1187 Lo = DAG.getNode(LanaiISD::LO, DL, MVT::i32, Lo)
[all...] |
| /src/external/apache2/llvm/dist/llvm/include/llvm/IR/ |
| Intrinsics.h | 197 unsigned short Lo) {
198 unsigned Field = Hi << 16 | Lo;
|
| MDBuilder.h | 86 /// Return metadata describing the range [Lo, Hi).
87 MDNode *createRange(const APInt &Lo, const APInt &Hi);
89 /// Return metadata describing the range [Lo, Hi).
90 MDNode *createRange(Constant *Lo, Constant *Hi);
|
| /src/external/apache2/llvm/dist/llvm/lib/MC/ |
| MCObjectStreamer.cpp | 129 // tree for (Hi - Lo) when Hi and Lo are offsets into the same fragment.
131 absoluteSymbolDiff(MCAssembler &Asm, const MCSymbol *Hi, const MCSymbol *Lo) {
132 assert(Hi && Lo);
136 if (!Hi->getFragment() || Hi->getFragment() != Lo->getFragment() ||
137 Hi->isVariable() || Lo->isVariable())
140 return Hi->getOffset() - Lo->getOffset();
144 const MCSymbol *Lo,
146 if (Optional<uint64_t> Diff = absoluteSymbolDiff(getAssembler(), Hi, Lo)) {
150 MCStreamer::emitAbsoluteSymbolDiff(Hi, Lo, Size)
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/CodeGen/ |
| SwitchLoweringUtils.cpp | 76 const APInt &Lo = Clusters[i].Low->getValue();
77 TotalCases[i] = (Hi - Lo).getLimitedValue() + 1;
430 uint64_t Lo = (Clusters[i].Low->getValue() - LowBound).getZExtValue();
432 assert(Hi >= Lo && Hi < 64 && "Invalid bit case!");
433 CB->Mask |= (-1ULL >> (63 - (Hi - Lo))) << Lo;
434 CB->Bits += Hi - Lo + 1;
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/ |
| HexagonVectorCombine.cpp | 93 Value *vlalignb(IRBuilder<> &Builder, Value *Lo, Value *Hi, Value *Amt) const;
94 Value *vralignb(IRBuilder<> &Builder, Value *Lo, Value *Hi, Value *Amt) const;
127 Value *getElementRange(IRBuilder<> &Builder, Value *Lo, Value *Hi, int Start,
1028 auto HexagonVectorCombine::vlalignb(IRBuilder<> &Builder, Value *Lo, Value *Hi,
1030 assert(Lo->getType() == Hi->getType() && "Argument type mismatch");
1036 return getElementRange(Builder, Lo, Hi, VecLen - IntAmt->getSExtValue(),
1046 {Hi, Lo, Amt});
1050 Value *Pair = concat(Builder, {Lo, Hi});
1057 return vralignb(Builder, Lo, Hi, Sub);
1062 auto HexagonVectorCombine::vralignb(IRBuilder<> &Builder, Value *Lo, Value *Hi
[all...] |
| /src/external/apache2/llvm/dist/llvm/include/llvm/ProfileData/ |
| GCOV.h | 163 uint32_t Lo, Hi;
164 if (!readInt(Lo) || !readInt(Hi))
166 Val = ((uint64_t)Hi << 32) | Lo;
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/Sparc/ |
| SparcISelDAGToDAG.cpp | 104 if (Addr.getOperand(0).getOpcode() == SPISD::Lo) {
109 if (Addr.getOperand(1).getOpcode() == SPISD::Lo) {
131 if (Addr.getOperand(0).getOpcode() == SPISD::Lo ||
132 Addr.getOperand(1).getOpcode() == SPISD::Lo)
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/ |
| AMDGPUISelDAGToDAG.cpp | 411 SDValue Lo = N->getOperand(0);
416 // build_vector lo, (load ptr) -> load_d16_hi ptr, lo
417 // build_vector lo, (zextload ptr from i8) -> load_d16_hi_u8 ptr, lo
418 // build_vector lo, (sextload ptr from i8) -> load_d16_hi_i8 ptr, lo
422 if (LdHi && Hi.hasOneUse() && !LdHi->isPredecessorOf(Lo.getNode())) {
425 SDValue TiedIn = CurDAG->getNode(ISD::SCALAR_TO_VECTOR, SDLoc(N), VT, Lo);
451 LoadSDNode *LdLo = dyn_cast<LoadSDNode>(stripBitcast(Lo));
[all...] |
