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    Searched refs:LoOpc (Results 1 - 6 of 6) sorted by relevancy

  /src/external/apache2/llvm/dist/llvm/lib/Target/Mips/
MipsSEInstrInfo.h 101 unsigned LoOpc, unsigned HiOpc,
MipsSEInstrInfo.cpp 729 unsigned LoOpc,
740 MachineInstrBuilder LoInst = BuildMI(MBB, I, DL, get(LoOpc));
  /src/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/
HexagonCopyToCombine.cpp 189 unsigned LoOpc = LowRegInst.getOpcode();
202 verifyOpc(LoOpc);
204 if (HiOpc == Hexagon::V6_vassign || LoOpc == Hexagon::V6_vassign)
205 return HiOpc == LoOpc;
  /src/external/apache2/llvm/dist/llvm/lib/CodeGen/SelectionDAG/
LegalizeIntegerTypes.cpp 2521 ISD::NodeType LoOpc;
2523 std::tie(CondC, LoOpc) = getExpandedMinMaxOps(N->getOpcode());
2546 SDValue LoMinMax = DAG.getNode(LoOpc, DL, NVT, {LHSL, RHSL});
  /src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/
SIISelLowering.cpp 3932 unsigned LoOpc = IsAdd ? AMDGPU::S_ADD_U32 : AMDGPU::S_SUB_U32;
3934 BuildMI(*BB, MI, DL, TII->get(LoOpc), DestSub0).add(Src0Sub0).add(Src1Sub0);
3987 unsigned LoOpc = IsAdd ? AMDGPU::V_ADD_CO_U32_e64 : AMDGPU::V_SUB_CO_U32_e64;
3988 MachineInstr *LoHalf = BuildMI(*BB, MI, DL, TII->get(LoOpc), DestSub0)
SIInstrInfo.cpp 6418 unsigned LoOpc = IsAdd ? AMDGPU::V_ADD_CO_U32_e64 : AMDGPU::V_SUB_CO_U32_e64;
6420 BuildMI(MBB, MII, DL, get(LoOpc), DestSub0)

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