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    Searched refs:Load1 (Results 1 - 13 of 13) sorted by relevancy

  /src/external/apache2/llvm/dist/llvm/lib/Target/X86/
X86InstrInfo.h 420 bool areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2, int64_t &Offset1,
437 /// have already been scheduled after Load1.
438 bool shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2, int64_t Offset1,
X86InstrInfo.cpp 6548 X86InstrInfo::areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2,
6550 if (!Load1->isMachineOpcode() || !Load2->isMachineOpcode())
6552 unsigned Opc1 = Load1->getMachineOpcode();
6723 return Load1->getOperand(I) == Load2->getOperand(I);
6736 auto Disp1 = dyn_cast<ConstantSDNode>(Load1->getOperand(X86::AddrDisp));
6746 bool X86InstrInfo::shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2,
6753 unsigned Opc1 = Load1->getMachineOpcode();
6768 EVT VT = Load1->getValueType(0);
X86ISelLowering.cpp 8752 // Combine a vector ops (shuffles etc.) that is equal to build_vector load1,
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  /src/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/
TargetInstrInfo.h 1296 virtual bool areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2,
1309 /// have already been scheduled after Load1.
1310 virtual bool shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2,
  /src/external/apache2/llvm/dist/llvm/lib/Target/ARM/
ARMBaseInstrInfo.h 247 bool areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2, int64_t &Offset1,
257 /// have already been scheduled after Load1.
258 bool shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2,
ARMBaseInstrInfo.cpp 1924 bool ARMBaseInstrInfo::areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2,
1930 if (!Load1->isMachineOpcode() || !Load2->isMachineOpcode())
1933 switch (Load1->getMachineOpcode()) {
1975 if (Load1->getOperand(0) != Load2->getOperand(0) ||
1976 Load1->getOperand(4) != Load2->getOperand(4))
1980 if (Load1->getOperand(3) != Load2->getOperand(3))
1984 if (isa<ConstantSDNode>(Load1->getOperand(1)) &&
1986 Offset1 = cast<ConstantSDNode>(Load1->getOperand(1))->getSExtValue();
2001 /// have already been scheduled after Load1.
2005 bool ARMBaseInstrInfo::shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2
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  /src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/
SIInstrInfo.h 184 bool areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2,
198 bool shouldScheduleLoadsNear(SDNode *Load0, SDNode *Load1, int64_t Offset0,
SIInstrInfo.cpp 129 bool SIInstrInfo::areLoadsFromSameBasePtr(SDNode *Load0, SDNode *Load1,
132 if (!Load0->isMachineOpcode() || !Load1->isMachineOpcode())
136 unsigned Opc1 = Load1->getMachineOpcode();
145 if (getNumOperandsNoGlue(Load0) != getNumOperandsNoGlue(Load1))
149 if (Load0->getOperand(0) != Load1->getOperand(0))
167 Offset1 = cast<ConstantSDNode>(Load1->getOperand(Offset1Idx))->getZExtValue();
177 assert(getNumOperandsNoGlue(Load0) == getNumOperandsNoGlue(Load1));
180 if (Load0->getOperand(0) != Load1->getOperand(0))
186 dyn_cast<ConstantSDNode>(Load1->getOperand(1));
200 if (!nodesHaveSameOperandValue(Load0, Load1, AMDGPU::OpName::soffset) |
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AMDGPURegisterBankInfo.cpp 1192 auto Load1 = B.buildLoadFromOffset(Part32, PtrReg, *MMO, 8);
1196 B.buildInsert(MI.getOperand(0), Ins0, Load1, 64);
  /src/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/
HexagonISelLoweringHVX.cpp 1829 SDValue Load1 = DAG.getLoad(SingleTy, dl, Chain, Base1, MOp1);
1831 { DAG.getNode(ISD::CONCAT_VECTORS, dl, MemTy, Load0, Load1),
1833 Load0.getValue(1), Load1.getValue(1)) }, dl);
HexagonISelLowering.cpp 3023 SDValue Load1 = DAG.getLoad(LoadTy, dl, Chain, Base1, WideMMO);
3026 {Load1, Load0, BaseNoOff.getOperand(0)});
3028 Load0.getValue(1), Load1.getValue(1));
  /src/external/apache2/llvm/dist/llvm/lib/Transforms/Instrumentation/
DataFlowSanitizer.cpp 2357 Value *Load1 =
2359 return {combineShadows(Load, Load1, Pos), Origin};
  /src/external/apache2/llvm/dist/llvm/lib/CodeGen/SelectionDAG/
DAGCombiner.cpp 10231 LoadSDNode *Load1 = cast<LoadSDNode>(Op1);
10233 if (!TLI.isLoadExtLegal(ExtLoadOpcode, VT, Load1->getMemoryVT()) ||

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