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      1 /*	$NetBSD: smu9_driver_if.h,v 1.2 2021/12/18 23:45:27 riastradh Exp $	*/
      2 
      3 /*
      4  * Copyright 2017 Advanced Micro Devices, Inc.
      5  *
      6  * Permission is hereby granted, free of charge, to any person obtaining a
      7  * copy of this software and associated documentation files (the "Software"),
      8  * to deal in the Software without restriction, including without limitation
      9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
     10  * and/or sell copies of the Software, and to permit persons to whom the
     11  * Software is furnished to do so, subject to the following conditions:
     12  *
     13  * The above copyright notice and this permission notice shall be included in
     14  * all copies or substantial portions of the Software.
     15  *
     16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
     17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
     18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
     19  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
     20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
     21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
     22  * OTHER DEALINGS IN THE SOFTWARE.
     23  *
     24  */
     25 
     26 #ifndef VEGA12_SMU9_DRIVER_IF_H
     27 #define VEGA12_SMU9_DRIVER_IF_H
     28 
     29 /**** IMPORTANT ***
     30  * SMU TEAM: Always increment the interface version if
     31  * any structure is changed in this file
     32  */
     33 #define SMU9_DRIVER_IF_VERSION 0x10
     34 
     35 #define PPTABLE_V12_SMU_VERSION 1
     36 
     37 #define NUM_GFXCLK_DPM_LEVELS  16
     38 #define NUM_VCLK_DPM_LEVELS    8
     39 #define NUM_DCLK_DPM_LEVELS    8
     40 #define NUM_ECLK_DPM_LEVELS    8
     41 #define NUM_MP0CLK_DPM_LEVELS  2
     42 #define NUM_UCLK_DPM_LEVELS    4
     43 #define NUM_SOCCLK_DPM_LEVELS  8
     44 #define NUM_DCEFCLK_DPM_LEVELS 8
     45 #define NUM_DISPCLK_DPM_LEVELS 8
     46 #define NUM_PIXCLK_DPM_LEVELS  8
     47 #define NUM_PHYCLK_DPM_LEVELS  8
     48 #define NUM_LINK_LEVELS        2
     49 
     50 #define MAX_GFXCLK_DPM_LEVEL  (NUM_GFXCLK_DPM_LEVELS  - 1)
     51 #define MAX_VCLK_DPM_LEVEL    (NUM_VCLK_DPM_LEVELS    - 1)
     52 #define MAX_DCLK_DPM_LEVEL    (NUM_DCLK_DPM_LEVELS    - 1)
     53 #define MAX_ECLK_DPM_LEVEL    (NUM_ECLK_DPM_LEVELS    - 1)
     54 #define MAX_MP0CLK_DPM_LEVEL  (NUM_MP0CLK_DPM_LEVELS  - 1)
     55 #define MAX_UCLK_DPM_LEVEL    (NUM_UCLK_DPM_LEVELS    - 1)
     56 #define MAX_SOCCLK_DPM_LEVEL  (NUM_SOCCLK_DPM_LEVELS  - 1)
     57 #define MAX_DCEFCLK_DPM_LEVEL (NUM_DCEFCLK_DPM_LEVELS - 1)
     58 #define MAX_DISPCLK_DPM_LEVEL (NUM_DISPCLK_DPM_LEVELS - 1)
     59 #define MAX_PIXCLK_DPM_LEVEL  (NUM_PIXCLK_DPM_LEVELS  - 1)
     60 #define MAX_PHYCLK_DPM_LEVEL  (NUM_PHYCLK_DPM_LEVELS  - 1)
     61 #define MAX_LINK_LEVEL        (NUM_LINK_LEVELS        - 1)
     62 
     63 
     64 #define PPSMC_GeminiModeNone   0
     65 #define PPSMC_GeminiModeMaster 1
     66 #define PPSMC_GeminiModeSlave  2
     67 
     68 
     69 #define FEATURE_DPM_PREFETCHER_BIT      0
     70 #define FEATURE_DPM_GFXCLK_BIT          1
     71 #define FEATURE_DPM_UCLK_BIT            2
     72 #define FEATURE_DPM_SOCCLK_BIT          3
     73 #define FEATURE_DPM_UVD_BIT             4
     74 #define FEATURE_DPM_VCE_BIT             5
     75 #define FEATURE_ULV_BIT                 6
     76 #define FEATURE_DPM_MP0CLK_BIT          7
     77 #define FEATURE_DPM_LINK_BIT            8
     78 #define FEATURE_DPM_DCEFCLK_BIT         9
     79 #define FEATURE_DS_GFXCLK_BIT           10
     80 #define FEATURE_DS_SOCCLK_BIT           11
     81 #define FEATURE_DS_LCLK_BIT             12
     82 #define FEATURE_PPT_BIT                 13
     83 #define FEATURE_TDC_BIT                 14
     84 #define FEATURE_THERMAL_BIT             15
     85 #define FEATURE_GFX_PER_CU_CG_BIT       16
     86 #define FEATURE_RM_BIT                  17
     87 #define FEATURE_DS_DCEFCLK_BIT          18
     88 #define FEATURE_ACDC_BIT                19
     89 #define FEATURE_VR0HOT_BIT              20
     90 #define FEATURE_VR1HOT_BIT              21
     91 #define FEATURE_FW_CTF_BIT              22
     92 #define FEATURE_LED_DISPLAY_BIT         23
     93 #define FEATURE_FAN_CONTROL_BIT         24
     94 #define FEATURE_GFX_EDC_BIT             25
     95 #define FEATURE_GFXOFF_BIT              26
     96 #define FEATURE_CG_BIT                  27
     97 #define FEATURE_ACG_BIT                 28
     98 #define FEATURE_SPARE_29_BIT            29
     99 #define FEATURE_SPARE_30_BIT            30
    100 #define FEATURE_SPARE_31_BIT            31
    101 
    102 #define NUM_FEATURES                    32
    103 
    104 #define FEATURE_DPM_PREFETCHER_MASK     (1 << FEATURE_DPM_PREFETCHER_BIT     )
    105 #define FEATURE_DPM_GFXCLK_MASK         (1 << FEATURE_DPM_GFXCLK_BIT         )
    106 #define FEATURE_DPM_UCLK_MASK           (1 << FEATURE_DPM_UCLK_BIT           )
    107 #define FEATURE_DPM_SOCCLK_MASK         (1 << FEATURE_DPM_SOCCLK_BIT         )
    108 #define FEATURE_DPM_UVD_MASK            (1 << FEATURE_DPM_UVD_BIT            )
    109 #define FEATURE_DPM_VCE_MASK            (1 << FEATURE_DPM_VCE_BIT            )
    110 #define FEATURE_ULV_MASK                (1 << FEATURE_ULV_BIT                )
    111 #define FEATURE_DPM_MP0CLK_MASK         (1 << FEATURE_DPM_MP0CLK_BIT         )
    112 #define FEATURE_DPM_LINK_MASK           (1 << FEATURE_DPM_LINK_BIT           )
    113 #define FEATURE_DPM_DCEFCLK_MASK        (1 << FEATURE_DPM_DCEFCLK_BIT        )
    114 #define FEATURE_DS_GFXCLK_MASK          (1 << FEATURE_DS_GFXCLK_BIT          )
    115 #define FEATURE_DS_SOCCLK_MASK          (1 << FEATURE_DS_SOCCLK_BIT          )
    116 #define FEATURE_DS_LCLK_MASK            (1 << FEATURE_DS_LCLK_BIT            )
    117 #define FEATURE_PPT_MASK                (1 << FEATURE_PPT_BIT                )
    118 #define FEATURE_TDC_MASK                (1 << FEATURE_TDC_BIT                )
    119 #define FEATURE_THERMAL_MASK            (1 << FEATURE_THERMAL_BIT            )
    120 #define FEATURE_GFX_PER_CU_CG_MASK      (1 << FEATURE_GFX_PER_CU_CG_BIT      )
    121 #define FEATURE_RM_MASK                 (1 << FEATURE_RM_BIT                 )
    122 #define FEATURE_DS_DCEFCLK_MASK         (1 << FEATURE_DS_DCEFCLK_BIT         )
    123 #define FEATURE_ACDC_MASK               (1 << FEATURE_ACDC_BIT               )
    124 #define FEATURE_VR0HOT_MASK             (1 << FEATURE_VR0HOT_BIT             )
    125 #define FEATURE_VR1HOT_MASK             (1 << FEATURE_VR1HOT_BIT             )
    126 #define FEATURE_FW_CTF_MASK             (1 << FEATURE_FW_CTF_BIT             )
    127 #define FEATURE_LED_DISPLAY_MASK        (1 << FEATURE_LED_DISPLAY_BIT        )
    128 #define FEATURE_FAN_CONTROL_MASK        (1 << FEATURE_FAN_CONTROL_BIT        )
    129 #define FEATURE_GFX_EDC_MASK            (1 << FEATURE_GFX_EDC_BIT            )
    130 #define FEATURE_GFXOFF_MASK             (1 << FEATURE_GFXOFF_BIT             )
    131 #define FEATURE_CG_MASK                 (1 << FEATURE_CG_BIT                 )
    132 #define FEATURE_ACG_MASK          (1 << FEATURE_ACG_BIT)
    133 #define FEATURE_SPARE_29_MASK           (1 << FEATURE_SPARE_29_BIT           )
    134 #define FEATURE_SPARE_30_MASK           (1 << FEATURE_SPARE_30_BIT           )
    135 #define FEATURE_SPARE_31_MASK           (1 << FEATURE_SPARE_31_BIT           )
    136 
    137 
    138 #define DPM_OVERRIDE_DISABLE_SOCCLK_PID             0x00000001
    139 #define DPM_OVERRIDE_DISABLE_UCLK_PID               0x00000002
    140 #define DPM_OVERRIDE_ENABLE_VOLT_LINK_UVD_SOCCLK    0x00000004
    141 #define DPM_OVERRIDE_ENABLE_VOLT_LINK_UVD_UCLK      0x00000008
    142 #define DPM_OVERRIDE_ENABLE_FREQ_LINK_VCLK_SOCCLK   0x00000010
    143 #define DPM_OVERRIDE_ENABLE_FREQ_LINK_VCLK_UCLK     0x00000020
    144 #define DPM_OVERRIDE_ENABLE_FREQ_LINK_DCLK_SOCCLK   0x00000040
    145 #define DPM_OVERRIDE_ENABLE_FREQ_LINK_DCLK_UCLK     0x00000080
    146 #define DPM_OVERRIDE_ENABLE_VOLT_LINK_VCE_SOCCLK    0x00000100
    147 #define DPM_OVERRIDE_ENABLE_VOLT_LINK_VCE_UCLK      0x00000200
    148 #define DPM_OVERRIDE_ENABLE_FREQ_LINK_ECLK_SOCCLK   0x00000400
    149 #define DPM_OVERRIDE_ENABLE_FREQ_LINK_ECLK_UCLK     0x00000800
    150 #define DPM_OVERRIDE_ENABLE_FREQ_LINK_GFXCLK_SOCCLK 0x00001000
    151 #define DPM_OVERRIDE_ENABLE_FREQ_LINK_GFXCLK_UCLK   0x00002000
    152 #define DPM_OVERRIDE_ENABLE_GFXOFF_GFXCLK_SWITCH    0x00004000
    153 #define DPM_OVERRIDE_ENABLE_GFXOFF_SOCCLK_SWITCH    0x00008000
    154 #define DPM_OVERRIDE_ENABLE_GFXOFF_UCLK_SWITCH      0x00010000
    155 
    156 
    157 #define VR_MAPPING_VR_SELECT_MASK  0x01
    158 #define VR_MAPPING_VR_SELECT_SHIFT 0x00
    159 
    160 #define VR_MAPPING_PLANE_SELECT_MASK  0x02
    161 #define VR_MAPPING_PLANE_SELECT_SHIFT 0x01
    162 
    163 
    164 #define PSI_SEL_VR0_PLANE0_PSI0  0x01
    165 #define PSI_SEL_VR0_PLANE0_PSI1  0x02
    166 #define PSI_SEL_VR0_PLANE1_PSI0  0x04
    167 #define PSI_SEL_VR0_PLANE1_PSI1  0x08
    168 #define PSI_SEL_VR1_PLANE0_PSI0  0x10
    169 #define PSI_SEL_VR1_PLANE0_PSI1  0x20
    170 #define PSI_SEL_VR1_PLANE1_PSI0  0x40
    171 #define PSI_SEL_VR1_PLANE1_PSI1  0x80
    172 
    173 
    174 #define THROTTLER_STATUS_PADDING_BIT      0
    175 #define THROTTLER_STATUS_TEMP_EDGE_BIT    1
    176 #define THROTTLER_STATUS_TEMP_HOTSPOT_BIT 2
    177 #define THROTTLER_STATUS_TEMP_HBM_BIT     3
    178 #define THROTTLER_STATUS_TEMP_VR_GFX_BIT  4
    179 #define THROTTLER_STATUS_TEMP_VR_MEM_BIT  5
    180 #define THROTTLER_STATUS_TEMP_LIQUID_BIT  6
    181 #define THROTTLER_STATUS_TEMP_PLX_BIT     7
    182 #define THROTTLER_STATUS_TEMP_SKIN_BIT    8
    183 #define THROTTLER_STATUS_TDC_GFX_BIT      9
    184 #define THROTTLER_STATUS_TDC_SOC_BIT      10
    185 #define THROTTLER_STATUS_PPT_BIT          11
    186 #define THROTTLER_STATUS_FIT_BIT          12
    187 #define THROTTLER_STATUS_PPM_BIT          13
    188 
    189 
    190 #define TABLE_TRANSFER_OK         0x0
    191 #define TABLE_TRANSFER_FAILED     0xFF
    192 
    193 
    194 #define WORKLOAD_DEFAULT_BIT              0
    195 #define WORKLOAD_PPLIB_FULL_SCREEN_3D_BIT 1
    196 #define WORKLOAD_PPLIB_POWER_SAVING_BIT   2
    197 #define WORKLOAD_PPLIB_VIDEO_BIT          3
    198 #define WORKLOAD_PPLIB_VR_BIT             4
    199 #define WORKLOAD_PPLIB_COMPUTE_BIT        5
    200 #define WORKLOAD_PPLIB_CUSTOM_BIT         6
    201 #define WORKLOAD_PPLIB_COUNT              7
    202 
    203 typedef struct {
    204   uint32_t a;
    205   uint32_t b;
    206   uint32_t c;
    207 } QuadraticInt_t;
    208 
    209 typedef struct {
    210   uint32_t m;
    211   uint32_t b;
    212 } LinearInt_t;
    213 
    214 typedef struct {
    215   uint32_t a;
    216   uint32_t b;
    217   uint32_t c;
    218 } DroopInt_t;
    219 
    220 typedef enum {
    221   PPCLK_GFXCLK,
    222   PPCLK_VCLK,
    223   PPCLK_DCLK,
    224   PPCLK_ECLK,
    225   PPCLK_SOCCLK,
    226   PPCLK_UCLK,
    227   PPCLK_DCEFCLK,
    228   PPCLK_DISPCLK,
    229   PPCLK_PIXCLK,
    230   PPCLK_PHYCLK,
    231   PPCLK_COUNT,
    232 } PPCLK_e;
    233 
    234 enum {
    235   VOLTAGE_MODE_AVFS,
    236   VOLTAGE_MODE_AVFS_SS,
    237   VOLTAGE_MODE_SS,
    238   VOLTAGE_MODE_COUNT,
    239 };
    240 
    241 typedef struct {
    242   uint8_t        VoltageMode;
    243   uint8_t        SnapToDiscrete;
    244   uint8_t        NumDiscreteLevels;
    245   uint8_t        padding;
    246   LinearInt_t    ConversionToAvfsClk;
    247   QuadraticInt_t SsCurve;
    248 } DpmDescriptor_t;
    249 
    250 typedef struct {
    251   uint32_t Version;
    252 
    253 
    254   uint32_t FeaturesToRun[2];
    255 
    256 
    257   uint16_t SocketPowerLimitAc0;
    258   uint16_t SocketPowerLimitAc0Tau;
    259   uint16_t SocketPowerLimitAc1;
    260   uint16_t SocketPowerLimitAc1Tau;
    261   uint16_t SocketPowerLimitAc2;
    262   uint16_t SocketPowerLimitAc2Tau;
    263   uint16_t SocketPowerLimitAc3;
    264   uint16_t SocketPowerLimitAc3Tau;
    265   uint16_t SocketPowerLimitDc;
    266   uint16_t SocketPowerLimitDcTau;
    267   uint16_t TdcLimitSoc;
    268   uint16_t TdcLimitSocTau;
    269   uint16_t TdcLimitGfx;
    270   uint16_t TdcLimitGfxTau;
    271 
    272   uint16_t TedgeLimit;
    273   uint16_t ThotspotLimit;
    274   uint16_t ThbmLimit;
    275   uint16_t Tvr_gfxLimit;
    276   uint16_t Tvr_memLimit;
    277   uint16_t Tliquid1Limit;
    278   uint16_t Tliquid2Limit;
    279   uint16_t TplxLimit;
    280   uint32_t FitLimit;
    281 
    282   uint16_t PpmPowerLimit;
    283   uint16_t PpmTemperatureThreshold;
    284 
    285   uint8_t  MemoryOnPackage;
    286   uint8_t  padding8_limits[3];
    287 
    288 
    289   uint16_t  UlvVoltageOffsetSoc;
    290   uint16_t  UlvVoltageOffsetGfx;
    291 
    292   uint8_t  UlvSmnclkDid;
    293   uint8_t  UlvMp1clkDid;
    294   uint8_t  UlvGfxclkBypass;
    295   uint8_t  Padding234;
    296 
    297 
    298   uint16_t     MinVoltageGfx;
    299   uint16_t     MinVoltageSoc;
    300   uint16_t     MaxVoltageGfx;
    301   uint16_t     MaxVoltageSoc;
    302 
    303   uint16_t     LoadLineResistance;
    304   uint16_t     LoadLine_padding;
    305 
    306 
    307   DpmDescriptor_t DpmDescriptor[PPCLK_COUNT];
    308 
    309   uint16_t       FreqTableGfx      [NUM_GFXCLK_DPM_LEVELS  ];
    310   uint16_t       FreqTableVclk     [NUM_VCLK_DPM_LEVELS    ];
    311   uint16_t       FreqTableDclk     [NUM_DCLK_DPM_LEVELS    ];
    312   uint16_t       FreqTableEclk     [NUM_ECLK_DPM_LEVELS    ];
    313   uint16_t       FreqTableSocclk   [NUM_SOCCLK_DPM_LEVELS  ];
    314   uint16_t       FreqTableUclk     [NUM_UCLK_DPM_LEVELS    ];
    315   uint16_t       FreqTableDcefclk  [NUM_DCEFCLK_DPM_LEVELS ];
    316   uint16_t       FreqTableDispclk  [NUM_DISPCLK_DPM_LEVELS ];
    317   uint16_t       FreqTablePixclk   [NUM_PIXCLK_DPM_LEVELS  ];
    318   uint16_t       FreqTablePhyclk   [NUM_PHYCLK_DPM_LEVELS  ];
    319 
    320   uint16_t       DcModeMaxFreq     [PPCLK_COUNT            ];
    321 
    322 
    323   uint16_t       Mp0clkFreq        [NUM_MP0CLK_DPM_LEVELS];
    324   uint16_t       Mp0DpmVoltage     [NUM_MP0CLK_DPM_LEVELS];
    325 
    326 
    327   uint16_t        GfxclkFidle;
    328   uint16_t        GfxclkSlewRate;
    329   uint16_t        CksEnableFreq;
    330   uint16_t        Padding789;
    331   QuadraticInt_t  CksVoltageOffset;
    332   uint16_t        AcgThresholdFreqHigh;
    333   uint16_t        AcgThresholdFreqLow;
    334   uint16_t        GfxclkDsMaxFreq;
    335   uint8_t         Padding456[2];
    336 
    337 
    338   uint8_t      LowestUclkReservedForUlv;
    339   uint8_t      Padding8_Uclk[3];
    340 
    341 
    342   uint8_t      PcieGenSpeed[NUM_LINK_LEVELS];
    343   uint8_t      PcieLaneCount[NUM_LINK_LEVELS];
    344   uint16_t     LclkFreq[NUM_LINK_LEVELS];
    345 
    346 
    347   uint16_t     EnableTdpm;
    348   uint16_t     TdpmHighHystTemperature;
    349   uint16_t     TdpmLowHystTemperature;
    350   uint16_t     GfxclkFreqHighTempLimit;
    351 
    352 
    353   uint16_t     FanStopTemp;
    354   uint16_t     FanStartTemp;
    355 
    356   uint16_t     FanGainEdge;
    357   uint16_t     FanGainHotspot;
    358   uint16_t     FanGainLiquid;
    359   uint16_t     FanGainVrVddc;
    360   uint16_t     FanGainVrMvdd;
    361   uint16_t     FanGainPlx;
    362   uint16_t     FanGainHbm;
    363   uint16_t     FanPwmMin;
    364   uint16_t     FanAcousticLimitRpm;
    365   uint16_t     FanThrottlingRpm;
    366   uint16_t     FanMaximumRpm;
    367   uint16_t     FanTargetTemperature;
    368   uint16_t     FanTargetGfxclk;
    369   uint8_t      FanZeroRpmEnable;
    370   uint8_t      FanTachEdgePerRev;
    371 
    372 
    373 
    374   int16_t      FuzzyFan_ErrorSetDelta;
    375   int16_t      FuzzyFan_ErrorRateSetDelta;
    376   int16_t      FuzzyFan_PwmSetDelta;
    377   uint16_t     FuzzyFan_Reserved;
    378 
    379 
    380 
    381 
    382   uint8_t           OverrideAvfsGb;
    383   uint8_t           Padding8_Avfs[3];
    384 
    385   QuadraticInt_t    qAvfsGb;
    386   DroopInt_t        dBtcGbGfxCksOn;
    387   DroopInt_t        dBtcGbGfxCksOff;
    388   DroopInt_t        dBtcGbGfxAcg;
    389   DroopInt_t        dBtcGbSoc;
    390   LinearInt_t       qAgingGbGfx;
    391   LinearInt_t       qAgingGbSoc;
    392 
    393   QuadraticInt_t    qStaticVoltageOffsetGfx;
    394   QuadraticInt_t    qStaticVoltageOffsetSoc;
    395 
    396   uint16_t          DcTolGfx;
    397   uint16_t          DcTolSoc;
    398 
    399   uint8_t           DcBtcGfxEnabled;
    400   uint8_t           DcBtcSocEnabled;
    401   uint8_t           Padding8_GfxBtc[2];
    402 
    403   uint16_t          DcBtcGfxMin;
    404   uint16_t          DcBtcGfxMax;
    405 
    406   uint16_t          DcBtcSocMin;
    407   uint16_t          DcBtcSocMax;
    408 
    409 
    410 
    411   uint32_t          DebugOverrides;
    412   QuadraticInt_t    ReservedEquation0;
    413   QuadraticInt_t    ReservedEquation1;
    414   QuadraticInt_t    ReservedEquation2;
    415   QuadraticInt_t    ReservedEquation3;
    416 
    417   uint16_t     MinVoltageUlvGfx;
    418   uint16_t     MinVoltageUlvSoc;
    419 
    420   uint32_t     Reserved[14];
    421 
    422 
    423 
    424   uint8_t      Liquid1_I2C_address;
    425   uint8_t      Liquid2_I2C_address;
    426   uint8_t      Vr_I2C_address;
    427   uint8_t      Plx_I2C_address;
    428 
    429   uint8_t      Liquid_I2C_LineSCL;
    430   uint8_t      Liquid_I2C_LineSDA;
    431   uint8_t      Vr_I2C_LineSCL;
    432   uint8_t      Vr_I2C_LineSDA;
    433 
    434   uint8_t      Plx_I2C_LineSCL;
    435   uint8_t      Plx_I2C_LineSDA;
    436   uint8_t      VrSensorPresent;
    437   uint8_t      LiquidSensorPresent;
    438 
    439   uint16_t     MaxVoltageStepGfx;
    440   uint16_t     MaxVoltageStepSoc;
    441 
    442   uint8_t      VddGfxVrMapping;
    443   uint8_t      VddSocVrMapping;
    444   uint8_t      VddMem0VrMapping;
    445   uint8_t      VddMem1VrMapping;
    446 
    447   uint8_t      GfxUlvPhaseSheddingMask;
    448   uint8_t      SocUlvPhaseSheddingMask;
    449   uint8_t      ExternalSensorPresent;
    450   uint8_t      Padding8_V;
    451 
    452 
    453   uint16_t     GfxMaxCurrent;
    454   int8_t       GfxOffset;
    455   uint8_t      Padding_TelemetryGfx;
    456 
    457   uint16_t     SocMaxCurrent;
    458   int8_t       SocOffset;
    459   uint8_t      Padding_TelemetrySoc;
    460 
    461   uint16_t     Mem0MaxCurrent;
    462   int8_t       Mem0Offset;
    463   uint8_t      Padding_TelemetryMem0;
    464 
    465   uint16_t     Mem1MaxCurrent;
    466   int8_t       Mem1Offset;
    467   uint8_t      Padding_TelemetryMem1;
    468 
    469 
    470   uint8_t      AcDcGpio;
    471   uint8_t      AcDcPolarity;
    472   uint8_t      VR0HotGpio;
    473   uint8_t      VR0HotPolarity;
    474 
    475   uint8_t      VR1HotGpio;
    476   uint8_t      VR1HotPolarity;
    477   uint8_t      Padding1;
    478   uint8_t      Padding2;
    479 
    480 
    481 
    482   uint8_t      LedPin0;
    483   uint8_t      LedPin1;
    484   uint8_t      LedPin2;
    485   uint8_t      padding8_4;
    486 
    487 
    488   uint8_t      PllGfxclkSpreadEnabled;
    489   uint8_t      PllGfxclkSpreadPercent;
    490   uint16_t     PllGfxclkSpreadFreq;
    491 
    492   uint8_t      UclkSpreadEnabled;
    493   uint8_t      UclkSpreadPercent;
    494   uint16_t     UclkSpreadFreq;
    495 
    496   uint8_t      SocclkSpreadEnabled;
    497   uint8_t      SocclkSpreadPercent;
    498   uint16_t     SocclkSpreadFreq;
    499 
    500   uint8_t      AcgGfxclkSpreadEnabled;
    501   uint8_t      AcgGfxclkSpreadPercent;
    502   uint16_t     AcgGfxclkSpreadFreq;
    503 
    504   uint8_t      Vr2_I2C_address;
    505   uint8_t      padding_vr2[3];
    506 
    507   uint32_t     BoardReserved[9];
    508 
    509 
    510   uint32_t     MmHubPadding[7];
    511 
    512 } PPTable_t;
    513 
    514 typedef struct {
    515 
    516   uint16_t     GfxclkAverageLpfTau;
    517   uint16_t     SocclkAverageLpfTau;
    518   uint16_t     UclkAverageLpfTau;
    519   uint16_t     GfxActivityLpfTau;
    520   uint16_t     UclkActivityLpfTau;
    521 
    522 
    523   uint32_t     MmHubPadding[7];
    524 } DriverSmuConfig_t;
    525 
    526 typedef struct {
    527 
    528   uint16_t      GfxclkFmin;
    529   uint16_t      GfxclkFmax;
    530   uint16_t      GfxclkFreq1;
    531   uint16_t      GfxclkOffsetVolt1;
    532   uint16_t      GfxclkFreq2;
    533   uint16_t      GfxclkOffsetVolt2;
    534   uint16_t      GfxclkFreq3;
    535   uint16_t      GfxclkOffsetVolt3;
    536   uint16_t      UclkFmax;
    537   int16_t       OverDrivePct;
    538   uint16_t      FanMaximumRpm;
    539   uint16_t      FanMinimumPwm;
    540   uint16_t      FanTargetTemperature;
    541   uint16_t      MaxOpTemp;
    542 
    543 } OverDriveTable_t;
    544 
    545 typedef struct {
    546   uint16_t CurrClock[PPCLK_COUNT];
    547   uint16_t AverageGfxclkFrequency;
    548   uint16_t AverageSocclkFrequency;
    549   uint16_t AverageUclkFrequency  ;
    550   uint16_t AverageGfxActivity    ;
    551   uint16_t AverageUclkActivity   ;
    552   uint8_t  CurrSocVoltageOffset  ;
    553   uint8_t  CurrGfxVoltageOffset  ;
    554   uint8_t  CurrMemVidOffset      ;
    555   uint8_t  Padding8              ;
    556   uint16_t CurrSocketPower       ;
    557   uint16_t TemperatureEdge       ;
    558   uint16_t TemperatureHotspot    ;
    559   uint16_t TemperatureHBM        ;
    560   uint16_t TemperatureVrGfx      ;
    561   uint16_t TemperatureVrMem      ;
    562   uint16_t TemperatureLiquid     ;
    563   uint16_t TemperaturePlx        ;
    564   uint32_t ThrottlerStatus       ;
    565 
    566   uint8_t  LinkDpmLevel;
    567   uint8_t  Padding[3];
    568 
    569 
    570   uint32_t     MmHubPadding[7];
    571 } SmuMetrics_t;
    572 
    573 typedef struct {
    574   uint16_t MinClock;
    575   uint16_t MaxClock;
    576   uint16_t MinUclk;
    577   uint16_t MaxUclk;
    578 
    579   uint8_t  WmSetting;
    580   uint8_t  Padding[3];
    581 } WatermarkRowGeneric_t;
    582 
    583 #define NUM_WM_RANGES 4
    584 
    585 typedef enum {
    586   WM_SOCCLK = 0,
    587   WM_DCEFCLK,
    588   WM_COUNT_PP,
    589 } WM_CLOCK_e;
    590 
    591 typedef struct {
    592 
    593   WatermarkRowGeneric_t WatermarkRow[WM_COUNT_PP][NUM_WM_RANGES];
    594 
    595   uint32_t     MmHubPadding[7];
    596 } Watermarks_t;
    597 
    598 typedef struct {
    599   uint16_t avgPsmCount[30];
    600   uint16_t minPsmCount[30];
    601   float    avgPsmVoltage[30];
    602   float    minPsmVoltage[30];
    603 
    604   uint32_t MmHubPadding[7];
    605 } AvfsDebugTable_t;
    606 
    607 typedef struct {
    608   uint8_t  AvfsEn;
    609   uint8_t  AvfsVersion;
    610   uint8_t  OverrideVFT;
    611   uint8_t  OverrideAvfsGb;
    612 
    613   uint8_t  OverrideTemperatures;
    614   uint8_t  OverrideVInversion;
    615   uint8_t  OverrideP2V;
    616   uint8_t  OverrideP2VCharzFreq;
    617 
    618   int32_t VFT0_m1;
    619   int32_t VFT0_m2;
    620   int32_t VFT0_b;
    621 
    622   int32_t VFT1_m1;
    623   int32_t VFT1_m2;
    624   int32_t VFT1_b;
    625 
    626   int32_t VFT2_m1;
    627   int32_t VFT2_m2;
    628   int32_t VFT2_b;
    629 
    630   int32_t AvfsGb0_m1;
    631   int32_t AvfsGb0_m2;
    632   int32_t AvfsGb0_b;
    633 
    634   int32_t AcBtcGb_m1;
    635   int32_t AcBtcGb_m2;
    636   int32_t AcBtcGb_b;
    637 
    638   uint32_t AvfsTempCold;
    639   uint32_t AvfsTempMid;
    640   uint32_t AvfsTempHot;
    641 
    642   uint32_t GfxVInversion;
    643   uint32_t SocVInversion;
    644 
    645   int32_t P2V_m1;
    646   int32_t P2V_m2;
    647   int32_t P2V_b;
    648 
    649   uint32_t P2VCharzFreq;
    650 
    651   uint32_t EnabledAvfsModules;
    652 
    653   uint32_t MmHubPadding[7];
    654 } AvfsFuseOverride_t;
    655 
    656 typedef struct {
    657 
    658   uint8_t   Gfx_ActiveHystLimit;
    659   uint8_t   Gfx_IdleHystLimit;
    660   uint8_t   Gfx_FPS;
    661   uint8_t   Gfx_MinActiveFreqType;
    662   uint8_t   Gfx_BoosterFreqType;
    663   uint8_t   Gfx_UseRlcBusy;
    664   uint16_t  Gfx_MinActiveFreq;
    665   uint16_t  Gfx_BoosterFreq;
    666   uint16_t  Gfx_PD_Data_time_constant;
    667   uint32_t  Gfx_PD_Data_limit_a;
    668   uint32_t  Gfx_PD_Data_limit_b;
    669   uint32_t  Gfx_PD_Data_limit_c;
    670   uint32_t  Gfx_PD_Data_error_coeff;
    671   uint32_t  Gfx_PD_Data_error_rate_coeff;
    672 
    673   uint8_t   Soc_ActiveHystLimit;
    674   uint8_t   Soc_IdleHystLimit;
    675   uint8_t   Soc_FPS;
    676   uint8_t   Soc_MinActiveFreqType;
    677   uint8_t   Soc_BoosterFreqType;
    678   uint8_t   Soc_UseRlcBusy;
    679   uint16_t  Soc_MinActiveFreq;
    680   uint16_t  Soc_BoosterFreq;
    681   uint16_t  Soc_PD_Data_time_constant;
    682   uint32_t  Soc_PD_Data_limit_a;
    683   uint32_t  Soc_PD_Data_limit_b;
    684   uint32_t  Soc_PD_Data_limit_c;
    685   uint32_t  Soc_PD_Data_error_coeff;
    686   uint32_t  Soc_PD_Data_error_rate_coeff;
    687 
    688   uint8_t   Mem_ActiveHystLimit;
    689   uint8_t   Mem_IdleHystLimit;
    690   uint8_t   Mem_FPS;
    691   uint8_t   Mem_MinActiveFreqType;
    692   uint8_t   Mem_BoosterFreqType;
    693   uint8_t   Mem_UseRlcBusy;
    694   uint16_t  Mem_MinActiveFreq;
    695   uint16_t  Mem_BoosterFreq;
    696   uint16_t  Mem_PD_Data_time_constant;
    697   uint32_t  Mem_PD_Data_limit_a;
    698   uint32_t  Mem_PD_Data_limit_b;
    699   uint32_t  Mem_PD_Data_limit_c;
    700   uint32_t  Mem_PD_Data_error_coeff;
    701   uint32_t  Mem_PD_Data_error_rate_coeff;
    702 
    703 } DpmActivityMonitorCoeffInt_t;
    704 
    705 
    706 
    707 
    708 #define TABLE_PPTABLE                 0
    709 #define TABLE_WATERMARKS              1
    710 #define TABLE_AVFS                    2
    711 #define TABLE_AVFS_PSM_DEBUG          3
    712 #define TABLE_AVFS_FUSE_OVERRIDE      4
    713 #define TABLE_PMSTATUSLOG             5
    714 #define TABLE_SMU_METRICS             6
    715 #define TABLE_DRIVER_SMU_CONFIG       7
    716 #define TABLE_ACTIVITY_MONITOR_COEFF  8
    717 #define TABLE_OVERDRIVE               9
    718 #define TABLE_COUNT                  10
    719 
    720 
    721 #define UCLK_SWITCH_SLOW 0
    722 #define UCLK_SWITCH_FAST 1
    723 
    724 
    725 #define SQ_Enable_MASK 0x1
    726 #define SQ_IR_MASK 0x2
    727 #define SQ_PCC_MASK 0x4
    728 #define SQ_EDC_MASK 0x8
    729 
    730 #define TCP_Enable_MASK 0x100
    731 #define TCP_IR_MASK 0x200
    732 #define TCP_PCC_MASK 0x400
    733 #define TCP_EDC_MASK 0x800
    734 
    735 #define TD_Enable_MASK 0x10000
    736 #define TD_IR_MASK 0x20000
    737 #define TD_PCC_MASK 0x40000
    738 #define TD_EDC_MASK 0x80000
    739 
    740 #define DB_Enable_MASK 0x1000000
    741 #define DB_IR_MASK 0x2000000
    742 #define DB_PCC_MASK 0x4000000
    743 #define DB_EDC_MASK 0x8000000
    744 
    745 #define SQ_Enable_SHIFT 0
    746 #define SQ_IR_SHIFT 1
    747 #define SQ_PCC_SHIFT 2
    748 #define SQ_EDC_SHIFT 3
    749 
    750 #define TCP_Enable_SHIFT 8
    751 #define TCP_IR_SHIFT 9
    752 #define TCP_PCC_SHIFT 10
    753 #define TCP_EDC_SHIFT 11
    754 
    755 #define TD_Enable_SHIFT 16
    756 #define TD_IR_SHIFT 17
    757 #define TD_PCC_SHIFT 18
    758 #define TD_EDC_SHIFT 19
    759 
    760 #define DB_Enable_SHIFT 24
    761 #define DB_IR_SHIFT 25
    762 #define DB_PCC_SHIFT 26
    763 #define DB_EDC_SHIFT 27
    764 
    765 #define REMOVE_FMAX_MARGIN_BIT     0x0
    766 #define REMOVE_DCTOL_MARGIN_BIT    0x1
    767 #define REMOVE_PLATFORM_MARGIN_BIT 0x2
    768 
    769 #endif
    770