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    Searched refs:LogicOpcode (Results 1 - 3 of 3) sorted by relevancy

  /src/external/apache2/llvm/dist/llvm/lib/CodeGen/GlobalISel/
CombinerHelper.cpp 1807 unsigned LogicOpcode = LogicMI->getOpcode();
1808 if (LogicOpcode != TargetOpcode::G_AND && LogicOpcode != TargetOpcode::G_OR &&
1809 LogicOpcode != TargetOpcode::G_XOR)
2871 unsigned LogicOpcode = MI.getOpcode();
2872 assert(LogicOpcode == TargetOpcode::G_AND ||
2873 LogicOpcode == TargetOpcode::G_OR ||
2874 LogicOpcode == TargetOpcode::G_XOR);
2904 if (!isLegalOrBeforeLegalizer({LogicOpcode, {XTy, YTy}}))
2939 InstructionBuildSteps LogicSteps(LogicOpcode, LogicBuildSteps)
    [all...]
  /src/external/apache2/llvm/dist/llvm/lib/CodeGen/SelectionDAG/
DAGCombiner.cpp 4786 unsigned LogicOpcode = N->getOpcode();
4788 assert((LogicOpcode == ISD::AND || LogicOpcode == ISD::OR ||
4789 LogicOpcode == ISD::XOR) && "Expected logic opcode");
4816 !TLI.isOperationLegalOrCustom(LogicOpcode, XVT))
4821 !TLI.isTypeDesirableForOp(LogicOpcode, XVT))
4824 SDValue Logic = DAG.getNode(LogicOpcode, DL, XVT, X, Y);
4838 if (LegalOperations && !TLI.isOperationLegal(LogicOpcode, XVT))
4846 SDValue Logic = DAG.getNode(LogicOpcode, DL, XVT, X, Y);
4858 SDValue Logic = DAG.getNode(LogicOpcode, DL, XVT, X, Y)
    [all...]
TargetLowering.cpp 3473 unsigned LogicOpcode = Cond == ISD::SETEQ ? ISD::AND : ISD::OR;
3474 return DAG.getNode(LogicOpcode, dl, VT, LHS, RHS);

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