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    Searched refs:MAL0_CFG_SR (Results 1 - 2 of 2) sorted by relevancy

  /src/sys/arch/powerpc/ibm4xx/dev/
mal.c 85 mtdcr(DCR_MAL0_CFG, MAL0_CFG_SR);
87 while (mfdcr(DCR_MAL0_CFG) & MAL0_CFG_SR) {
  /src/sys/arch/powerpc/include/ibm4xx/
dcr4xx.h 139 #define MAL0_CFG_SR 0x80000000 /* Software Reset */

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