HomeSort by: relevance | last modified time | path
    Searched refs:MASTER_COMM_CMD_REG (Results 1 - 5 of 5) sorted by relevancy

  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dce/
amdgpu_dce_dmcu.c 146 REG_UPDATE(MASTER_COMM_CMD_REG, MASTER_COMM_CMD_REG_BYTE0,
149 REG_UPDATE(MASTER_COMM_CMD_REG, MASTER_COMM_CMD_REG_BYTE0,
272 REG_UPDATE(MASTER_COMM_CMD_REG,
319 REG_UPDATE(MASTER_COMM_CMD_REG, MASTER_COMM_CMD_REG_BYTE0, PSR_SET_WAITLOOP);
371 REG_UPDATE(MASTER_COMM_CMD_REG, MASTER_COMM_CMD_REG_BYTE0,
410 REG_UPDATE(MASTER_COMM_CMD_REG, MASTER_COMM_CMD_REG_BYTE0,
493 REG_UPDATE(MASTER_COMM_CMD_REG, MASTER_COMM_CMD_REG_BYTE0,
552 REG_UPDATE(MASTER_COMM_CMD_REG, MASTER_COMM_CMD_REG_BYTE0,
555 REG_UPDATE(MASTER_COMM_CMD_REG, MASTER_COMM_CMD_REG_BYTE0,
696 REG_UPDATE(MASTER_COMM_CMD_REG,
    [all...]
dce_abm.h 41 SR(MASTER_COMM_CMD_REG), \
100 ABM_SF(MASTER_COMM_CMD_REG, MASTER_COMM_CMD_REG_BYTE0, mask_sh), \
101 ABM_SF(MASTER_COMM_CMD_REG, MASTER_COMM_CMD_REG_BYTE1, mask_sh), \
102 ABM_SF(MASTER_COMM_CMD_REG, MASTER_COMM_CMD_REG_BYTE2, mask_sh)
221 uint32_t MASTER_COMM_CMD_REG;
dce_dmcu.h 43 SR(MASTER_COMM_CMD_REG), \
60 SR(MASTER_COMM_CMD_REG), \
96 DMCU_SF(MASTER_COMM_CMD_REG, \
122 DMCU_SF(MASTER_COMM_CMD_REG, \
177 uint32_t MASTER_COMM_CMD_REG;
amdgpu_dce_abm.c 78 REG_UPDATE_2(MASTER_COMM_CMD_REG,
236 REG_UPDATE(MASTER_COMM_CMD_REG, MASTER_COMM_CMD_REG_BYTE0, MCP_BL_SET);
329 REG_UPDATE_2(MASTER_COMM_CMD_REG,
dce_link_encoder.h 123 uint32_t MASTER_COMM_CMD_REG;

Completed in 15 milliseconds