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Searched refs:MASTER_COMM_CNTL_REG__MASTER_COMM_INTERRUPT_MASK (Results 1 - 10 of 10) sorted by relevancy

/src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dce/
amdgpu_dce_dmcu.c	`65 #define MASTER_COMM_CNTL_REG__MASTER_COMM_INTERRUPT_MASK 0x00000001L`
/src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/dce/
dce_6_0_sh_mask.h	`7663 #define MASTER_COMM_CNTL_REG__MASTER_COMM_INTERRUPT_MASK 0x00000001L`
dce_8_0_sh_mask.h	`8153 #define MASTER_COMM_CNTL_REG__MASTER_COMM_INTERRUPT_MASK 0x1`
dce_10_0_sh_mask.h	`7217 #define MASTER_COMM_CNTL_REG__MASTER_COMM_INTERRUPT_MASK 0x1 [all...]`
dce_11_0_sh_mask.h	`7107 #define MASTER_COMM_CNTL_REG__MASTER_COMM_INTERRUPT_MASK 0x1 [all...]`
dce_11_2_sh_mask.h	`8219 #define MASTER_COMM_CNTL_REG__MASTER_COMM_INTERRUPT_MASK 0x1 [all...]`
dce_12_0_sh_mask.h	`5122 #define MASTER_COMM_CNTL_REG__MASTER_COMM_INTERRUPT_MASK 0x00000001L [all...]`
/src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/dcn/
dcn_1_0_sh_mask.h	`4141 #define MASTER_COMM_CNTL_REG__MASTER_COMM_INTERRUPT_MASK 0x00000001L [all...]`
dcn_2_0_0_sh_mask.h	`2915 #define MASTER_COMM_CNTL_REG__MASTER_COMM_INTERRUPT_MASK 0x00000001L [all...]`
dcn_2_1_0_sh_mask.h	`2647 #define MASTER_COMM_CNTL_REG__MASTER_COMM_INTERRUPT_MASK 0x00000001L [all...]`

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