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    Searched refs:MAX_MPCC (Results 1 - 6 of 6) sorted by relevancy

  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn20/
dcn20_mpc.h 91 uint32_t MPCC_TOP_GAIN[MAX_MPCC]; \
92 uint32_t MPCC_BOT_GAIN_INSIDE[MAX_MPCC]; \
93 uint32_t MPCC_BOT_GAIN_OUTSIDE[MAX_MPCC]; \
94 uint32_t MPCC_OGAM_RAMA_START_CNTL_B[MAX_MPCC]; \
95 uint32_t MPCC_OGAM_RAMA_START_CNTL_G[MAX_MPCC]; \
96 uint32_t MPCC_OGAM_RAMA_START_CNTL_R[MAX_MPCC]; \
97 uint32_t MPCC_OGAM_RAMA_SLOPE_CNTL_B[MAX_MPCC]; \
98 uint32_t MPCC_OGAM_RAMA_SLOPE_CNTL_G[MAX_MPCC]; \
99 uint32_t MPCC_OGAM_RAMA_SLOPE_CNTL_R[MAX_MPCC]; \
100 uint32_t MPCC_OGAM_RAMA_END_CNTL1_B[MAX_MPCC]; \
    [all...]
amdgpu_dcn20_mpc.c 585 for (i = 0; i < MAX_MPCC; i++)
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn10/
dcn10_mpc.h 51 uint32_t MPCC_TOP_SEL[MAX_MPCC]; \
52 uint32_t MPCC_BOT_SEL[MAX_MPCC]; \
53 uint32_t MPCC_CONTROL[MAX_MPCC]; \
54 uint32_t MPCC_STATUS[MAX_MPCC]; \
55 uint32_t MPCC_OPP_ID[MAX_MPCC]; \
56 uint32_t MPCC_BG_G_Y[MAX_MPCC]; \
57 uint32_t MPCC_BG_R_CR[MAX_MPCC]; \
58 uint32_t MPCC_BG_B_CB[MAX_MPCC]; \
59 uint32_t MPCC_SM_CONTROL[MAX_MPCC]; \
amdgpu_dcn10_mpc.c 498 for (i = 0; i < MAX_MPCC; i++)
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/inc/hw/
mpc.h 33 #define MAX_MPCC 6
124 struct mpcc mpcc_array[MAX_MPCC];
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/core/
amdgpu_dc_resource.c 1934 if (s.dpp_id < MAX_MPCC)
1937 if (s.bot_mpcc_id < MAX_MPCC)

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