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    Searched refs:MAX_REGULAR_DPM_NUMBER (Results 1 - 13 of 13) sorted by relevancy

  /src/sys/external/bsd/drm2/dist/drm/amd/powerplay/
vega20_ppt.h 34 #define MAX_REGULAR_DPM_NUMBER 16
101 struct vega20_dpm_level dpm_levels[MAX_REGULAR_DPM_NUMBER];
amdgpu_vega20_ppt.c 2310 if (table->count > MAX_REGULAR_DPM_NUMBER) {
2312 return MAX_REGULAR_DPM_NUMBER - 1;
  /src/sys/external/bsd/drm2/dist/drm/amd/powerplay/hwmgr/
vega10_hwmgr.h 124 #define MAX_REGULAR_DPM_NUMBER 8
138 struct vega10_dpm_level dpm_levels[MAX_REGULAR_DPM_NUMBER];
223 struct vega10_mclk_latency_entries entries[MAX_REGULAR_DPM_NUMBER];
288 struct phm_ppt_v1_clock_voltage_dependency_record entries[MAX_REGULAR_DPM_NUMBER];
293 struct phm_ppt_v1_voltage_lookup_record entries[MAX_REGULAR_DPM_NUMBER];
vega12_hwmgr.h 98 #define MAX_REGULAR_DPM_NUMBER 16
112 struct vega12_dpm_level dpm_levels[MAX_REGULAR_DPM_NUMBER];
117 uint32_t entries[MAX_REGULAR_DPM_NUMBER];
214 struct vega12_mclk_latency_entries entries[MAX_REGULAR_DPM_NUMBER];
287 entries[MAX_REGULAR_DPM_NUMBER];
smu7_hwmgr.h 97 #define MAX_REGULAR_DPM_NUMBER 8
102 struct smu7_dpm_level dpm_levels[MAX_REGULAR_DPM_NUMBER];
181 phm_ppt_v1_clock_voltage_dependency_record entries[MAX_REGULAR_DPM_NUMBER];
vega20_hwmgr.h 141 #define MAX_REGULAR_DPM_NUMBER 16
164 struct vega20_dpm_level dpm_levels[MAX_REGULAR_DPM_NUMBER];
169 uint32_t entries[MAX_REGULAR_DPM_NUMBER];
274 struct vega20_mclk_latency_entries entries[MAX_REGULAR_DPM_NUMBER];
349 entries[MAX_REGULAR_DPM_NUMBER];
smu10_hwmgr.h 177 #define MAX_REGULAR_DPM_NUMBER 8
186 struct smu10_mclk_latency_entries entries[MAX_REGULAR_DPM_NUMBER];
amdgpu_smu7_hwmgr.c 565 MAX_REGULAR_DPM_NUMBER);
645 MAX_REGULAR_DPM_NUMBER);
649 SMU_MAX_LEVELS_MEMORY), MAX_REGULAR_DPM_NUMBER);
655 MAX_REGULAR_DPM_NUMBER);
659 SMU_MAX_LEVELS_VDDCI), MAX_REGULAR_DPM_NUMBER);
665 MAX_REGULAR_DPM_NUMBER);
amdgpu_vega12_hwmgr.c 1026 PP_ASSERT_WITH_CODE(table->count <= MAX_REGULAR_DPM_NUMBER,
1028 return MAX_REGULAR_DPM_NUMBER - 1);
amdgpu_vega10_hwmgr.c 1748 while (i < MAX_REGULAR_DPM_NUMBER) {
3496 if (table->count <= MAX_REGULAR_DPM_NUMBER) {
3503 return MAX_REGULAR_DPM_NUMBER - 1;
amdgpu_vega20_hwmgr.c 1787 PP_ASSERT_WITH_CODE(table->count <= MAX_REGULAR_DPM_NUMBER,
1789 return MAX_REGULAR_DPM_NUMBER - 1);
  /src/sys/external/bsd/drm2/dist/drm/radeon/
ci_dpm.h 62 #define MAX_REGULAR_DPM_NUMBER 8
67 struct ci_dpm_level dpm_levels[MAX_REGULAR_DPM_NUMBER];
radeon_ci_dpm.c 3387 for (i = 0; i < MAX_REGULAR_DPM_NUMBER; i++)

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