| /src/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/MCTargetDesc/ |
| HexagonMCInstrInfo.h | 82 MCInst const &MCI);
86 bundleInstructions(MCInstrInfo const &MCII, MCInst const &MCI);
87 iterator_range<MCInst::const_iterator> bundleInstructions(MCInst const &MCI);
90 size_t bundleSize(MCInst const &MCI);
110 MCInst const &MCI);
113 unsigned getMemAccessSize(MCInstrInfo const &MCII, MCInst const &MCI);
116 unsigned getAddrMode(MCInstrInfo const &MCII, MCInst const &MCI);
118 MCInstrDesc const &getDesc(MCInstrInfo const &MCII, MCInst const &MCI);
132 unsigned short getExtendableOp(MCInstrInfo const &MCII, MCInst const &MCI);
136 MCInst const &MCI);
[all...] |
| HexagonMCInstrInfo.cpp | 89 MCInst const &MCI) {
92 MCI.getOperand(HexagonMCInstrInfo::getExtendableOp(MCII, MCI));
96 new (Context) MCInst(HexagonMCInstrInfo::deriveExtender(MCII, MCI, exOp));
97 XMCI->setLoc(MCI.getLoc());
104 MCInst const &MCI) {
105 assert(isBundle(MCI));
106 return make_range(Hexagon::PacketIterator(MCII, MCI),
107 Hexagon::PacketIterator(MCII, MCI, nullptr));
111 HexagonMCInstrInfo::bundleInstructions(MCInst const &MCI) {
[all...] |
| HexagonMCDuplexInfo.cpp | 189 unsigned HexagonMCInstrInfo::getDuplexCandidateGroup(MCInst const &MCI) {
192 switch (MCI.getOpcode()) {
201 DstReg = MCI.getOperand(0).getReg();
202 SrcReg = MCI.getOperand(1).getReg();
207 Hexagon::R29 == SrcReg && inRange<5, 2>(MCI, 2)) {
212 inRange<4, 2>(MCI, 2)) {
219 DstReg = MCI.getOperand(0).getReg();
220 SrcReg = MCI.getOperand(1).getReg();
223 inRange<4>(MCI, 2)) {
240 DstReg = MCI.getOperand(0).getReg()
[all...] |
| HexagonInstPrinter.cpp | 41 MCInst const &MCI = *I.getInst();
42 if (HexagonMCInstrInfo::isDuplex(MII, MCI)) {
43 printInstruction(MCI.getOperand(1).getInst(), Address, OS);
46 printInstruction(MCI.getOperand(0).getInst(), Address, OS);
48 printInstruction(&MCI, Address, OS);
49 HasExtender = HexagonMCInstrInfo::isImmext(MCI);
|
| HexagonMCCompound.cpp | 350 MCInst &MCI) {
351 assert(HexagonMCInstrInfo::isBundle(MCI));
354 MCI.begin() + HexagonMCInstrInfo::bundleInstructionsOffset;
355 J != MCI.end(); ++J) {
365 MCI.begin() + HexagonMCInstrInfo::bundleInstructionsOffset;
366 B != MCI.end(); ++B) {
383 MCI.erase(B);
400 MCContext &Context, MCInst &MCI) {
401 assert(HexagonMCInstrInfo::isBundle(MCI) &&
405 if (MCI.size() < 2
[all...] |
| HexagonMCChecker.cpp | 66 void HexagonMCChecker::initReg(MCInst const &MCI, unsigned R, unsigned &PredReg,
68 if (HexagonMCInstrInfo::isPredicated(MCII, MCI) && isPredicateRegister(R)) {
71 isTrue = HexagonMCInstrInfo::isPredicatedTrue(MCII, MCI);
74 if (HexagonMCInstrInfo::isPredicatedNew(MCII, MCI))
89 void HexagonMCChecker::init(MCInst const &MCI) {
90 const MCInstrDesc &MCID = HexagonMCInstrInfo::getDesc(MCII, MCI);
96 if (MCI.getOperand(i).isReg())
97 initReg(MCI, MCI.getOperand(i).getReg(), PredReg, isTrue);
99 initReg(MCI, MCID.getImplicitUses()[i], PredReg, isTrue)
[all...] |
| HexagonMCELFStreamer.cpp | 70 MCInst *MCI = const_cast<MCInst *>(I.getInst());
71 EmitSymbol(*MCI);
|
| HexagonMCCodeEmitter.h | 82 // Return parse bits for instruction `MCI' inside bundle `MCB'
83 uint32_t parseBits(size_t Last, MCInst const &MCB, MCInst const &MCI) const;
|
| HexagonAsmBackend.cpp | 580 MCInst &MCI = const_cast<MCInst &>(HexagonMCInstrInfo::instruction(
582 bool Relaxable = isInstRelaxable(MCI);
600 *RelaxTarget = &MCI;
638 *RelaxTarget = &MCI;
|
| /src/external/apache2/llvm/dist/llvm/include/llvm/MCA/ |
| InstrBuilder.h | 51 Expected<const InstrDesc &> createInstrDescImpl(const MCInst &MCI);
52 Expected<const InstrDesc &> getOrCreateInstrDesc(const MCInst &MCI);
57 void populateWrites(InstrDesc &ID, const MCInst &MCI, unsigned SchedClassID);
58 void populateReads(InstrDesc &ID, const MCInst &MCI, unsigned SchedClassID);
59 Error verifyInstrDesc(const InstrDesc &ID, const MCInst &MCI) const;
71 Expected<std::unique_ptr<Instruction>> createInstruction(const MCInst &MCI);
|
| Support.h | 32 InstructionError(std::string M, const T &MCI)
33 : Message(std::move(M)), Inst(MCI) {}
|
| /src/external/apache2/llvm/dist/llvm/lib/MCA/ |
| InstrBuilder.cpp | 221 static Error verifyOperands(const MCInstrDesc &MCDesc, const MCInst &MCI) {
225 for (I = 0, E = MCI.getNumOperands(); NumExplicitDefs && I < E; ++I) {
226 const MCOperand &Op = MCI.getOperand(I);
233 "Expected more register operand definitions.", MCI);
238 const MCOperand &Op = MCI.getOperand(MCDesc.getNumOperands() - 1);
239 if (I == MCI.getNumOperands() || !Op.isReg()) {
243 return make_error<InstructionError<MCInst>>(Message, MCI);
250 void InstrBuilder::populateWrites(InstrDesc &ID, const MCInst &MCI,
252 const MCInstrDesc &MCDesc = MCII.get(MCI.getOpcode());
306 unsigned NumVariadicOps = MCI.getNumOperands() - MCDesc.getNumOperands()
[all...] |
| /src/external/apache2/llvm/dist/llvm/tools/llvm-mca/Views/ |
| InstructionView.cpp | 22 StringRef InstructionView::printInstructionString(const llvm::MCInst &MCI) const {
24 MCIP.printInst(&MCI, 0, "", STI, InstrStream);
33 for (const auto &MCI : getSource()) {
34 StringRef Instruction = printInstructionString(MCI);
|
| InstructionView.h | 53 StringRef printInstructionString(const llvm::MCInst &MCI) const;
|
| ResourcePressureView.cpp | 159 for (const MCInst &MCI : Source) {
166 FOS << printInstructionString(MCI) << '\n';
|
| BottleneckAnalysis.h | 318 void printInstruction(formatted_raw_ostream &FOS, const MCInst &MCI,
|
| BottleneckAnalysis.cpp | 287 const MCInst &MCI,
292 FOS << printInstructionString(MCI);
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/ |
| HexagonMCInstLower.cpp | 107 MCInst *MCI = AP.OutContext.createMCInst();
108 MCI->setOpcode(MI->getOpcode());
109 assert(MCI->getOpcode() == static_cast<unsigned>(MI->getOpcode()) &&
110 "MCI opcode should have been set on construction");
175 MCI->addOperand(MCO);
177 AP.HexagonProcessInstruction(*MCI, *MI);
178 HexagonMCInstrInfo::extendIfNeeded(AP.OutContext, MCII, MCB, *MCI);
179 MCB.addOperand(MCOperand::createInst(MCI));
|
| /src/external/apache2/llvm/dist/llvm/tools/llvm-exegesis/lib/ |
| SchedClassResolution.h | 45 const MCInstrInfo &InstrInfo, const MCInst &MCI);
|
| SchedClassResolution.cpp | 222 const MCInst &MCI) {
225 SchedClassId = STI.resolveVariantSchedClass(SchedClassId, &MCI, &InstrInfo,
234 const MCInst &MCI) {
235 unsigned SchedClassId = InstrInfo.get(MCI.getOpcode()).getSchedClass();
240 ResolveVariantSchedClassId(SubtargetInfo, InstrInfo, SchedClassId, MCI);
|
| Analysis.cpp | 136 const MCInst &MCI = Point.keyInstruction();
139 *SubtargetInfo_, *InstrInfo_, MCI);
228 const MCInst &MCI = Point.keyInstruction();
233 MCI);
|
| /src/external/apache2/llvm/dist/llvm/lib/Analysis/ |
| Lint.cpp | 290 MemCpyInst *MCI = cast<MemCpyInst>(&I);
291 visitMemoryReference(I, MemoryLocation::getForDest(MCI),
292 MCI->getDestAlign(), nullptr, MemRef::Write);
293 visitMemoryReference(I, MemoryLocation::getForSource(MCI),
294 MCI->getSourceAlign(), nullptr, MemRef::Read);
301 dyn_cast<ConstantInt>(findValue(MCI->getLength(),
305 Assert(AA->alias(MCI->getSource(), Size, MCI->getDest(), Size) !=
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/AsmParser/ |
| HexagonAsmParser.cpp | 128 void canonicalizeImmediates(MCInst &MCI);
537 void HexagonAsmParser::canonicalizeImmediates(MCInst &MCI) {
539 NewInst.setOpcode(MCI.getOpcode());
540 for (MCOperand &I : MCI)
548 Warning(MCI.getLoc(), "Signed/Unsigned mismatch");
551 MCI = NewInst;
554 bool HexagonAsmParser::matchOneInstruction(MCInst &MCI, SMLoc IDLoc,
560 MatchInstructionImpl(InstOperands, MCI, ErrorInfo, MatchingInlineAsm);
562 MCI.setLoc(IDLoc);
563 canonicalizeImmediates(MCI);
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Transforms/Scalar/ |
| LoopIdiomRecognize.cpp | 216 bool processLoopMemCpy(MemCpyInst *MCI, const SCEV *BECount);
827 bool LoopIdiomRecognize::processLoopMemCpy(MemCpyInst *MCI,
830 if (MCI->isVolatile() || !isa<ConstantInt>(MCI->getLength()))
837 Value *Dest = MCI->getDest();
838 Value *Source = MCI->getSource();
853 uint64_t SizeInBytes = cast<ConstantInt>(MCI->getLength())->getZExtValue();
874 return OptimizationRemarkMissed(DEBUG_TYPE, "SizeStrideUnequal", MCI)
876 << ore::NV("Function", MCI->getFunction())
890 MCI->getDestAlign(), MCI->getSourceAlign()
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/IR/ |
| IRBuilder.cpp | 183 auto* MCI = cast<MemTransferInst>(CI);
185 MCI->setDestAlignment(*DstAlign);
187 MCI->setSourceAlignment(*SrcAlign);
221 auto *MCI = cast<MemCpyInlineInst>(CI);
223 MCI->setDestAlignment(*DstAlign);
225 MCI->setSourceAlignment(*SrcAlign);
|
