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    Searched refs:MCIF_WB_BUFMGR_VCE_CONTROL (Results 1 - 3 of 3) sorted by relevancy

  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn20/
amdgpu_dcn20_mmhubbub.c 204 REG_UPDATE(MCIF_WB_BUFMGR_VCE_CONTROL, MCIF_WB_BUFMGR_SLICE_SIZE, params->slice_lines-1);
222 REG_UPDATE(MCIF_WB_BUFMGR_VCE_CONTROL, MCIF_WB_BUFMGR_VCE_INT_EN, params->vce_int_en);
223 REG_UPDATE(MCIF_WB_BUFMGR_VCE_CONTROL, MCIF_WB_BUFMGR_VCE_SLICE_INT_EN, params->vce_slice_int_en);
dcn20_mmhubbub.h 94 SRI(MCIF_WB_BUFMGR_VCE_CONTROL, MCIF_WB, inst),\
476 uint32_t MCIF_WB_BUFMGR_VCE_CONTROL;\
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn10/
dcn10_dwb.h 80 SRI(MCIF_WB_BUFMGR_VCE_CONTROL, MCIF_WB, inst),\
243 uint32_t MCIF_WB_BUFMGR_VCE_CONTROL;

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